Abstract: A hardware cryptographic engine comprises a direct-memory-access (DMA) input module for receiving input data over a memory bus, and a cryptographic module. The cryptographic module comprises an input register having an input-register length, and circuitry configured to perform a cryptographic operation on data in the input register. The hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and alignment circuitry performing an alignment operation on input data in the input-alignment buffer. The hardware cryptographic engine is configured to pass input data, received by the DMA input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.

Abstract: A cryptographic module is switchable between a key-input mode and a data-input mode. In the key-input mode, the cryptographic module receives key data, key length information and first input data, combines an amount of the key data corresponding to the key length information with the first input data to produce combined data, wherein a key-influenced length of the combined data is the shortest length of the combined data that contains every data bit of the combined data whose value depends on the key data. It performs a cryptographic operation on the combined data to generate first output data and does not output any of the first output data until after the cryptographic operation has been applied to all of the key-influenced length of the combined data.

Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.

Abstract: A radio communication apparatus receives or generates a base address seed, and generates data-channel access addresses from the seed. Each access address corresponds to a respective data-channel identifier, and is generated by setting a bit at a common first bit position to the value of a bit at a first common predetermined bit position in the base address seed or in the respective data-channel identifier; by setting a bit at a common second bit position to the bitwise complement of this value; and by setting one or more remaining bit positions in dependence on values at one or more bit positions in the base address seed and one or more bit positions in the respective data-channel identifier that are not the first common predetermined bit position. The apparatus can send or receive a radio data packet comprising an access address from the generated set.

Abstract: An integrated circuit microprocessor device comprises a central processing unit (CPU) and a general purpose input or output subsystem (2) having at least one external connection (4). The external connection is configured to provide an input to or output from the device depending upon an associated setting in the general purpose input or output subsystem. At least one further module on the device is configured to be able to request at least a first or a second task which may control a state of the external connection, the general purpose input or output subsystem being configured, upon receipt of conflicting requests for the first and second tasks, to apply a predetermined priority to allow only one of the tasks to be applied to the external connection.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A radio receiver device is arranged to store samples of incoming data symbols in an indexed memory portion having a length of A+B+C. A first data buffer 20-1 has an initial address at index 0 and a final address at index A-1. A timing adjustment buffer 22 has an initial address at index A and a final address at index A+B?1. A second data buffer 20-2 has an initial address at an index A+B and a final address at an index A+B+C?1. A buffer switch pointer 24 has a trigger address between the index 0 and the index A+B?1, at which it triggers a switch 26 from the first to the second buffer. If the current address matches the trigger address, the current address is set to the index A+B. Otherwise, the current address is incremented. If there is a timing offset between local and network clocks, the trigger address is moved to reduce the offset.

Abstract: A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.

Abstract: A digital microprocessor device (2) has: a central processing unit; a memory (8); and an output signal module (4). The output signal module comprises: a counter (6) arranged to count to a predetermined count value; and at least one comparator (10a, 10b, 10c) arranged to change an output signal (14a, 14b, 14c) from a first output state to a second output state when the counter reaches a predetermined comparator value. The output signal module is arranged to load automatically from the memory at least one parameter selected from the group comprising: the predetermined count value, the predetermined comparator value and the first output state or the second output state, without receipt of an instruction from the central processing unit.

Abstract: An integrated circuit system comprises first and second processing modules. The first processing module comprises a first processor, clock and memory; and the second processing module comprises a second processor, clock and memory. The first processing module sends a time-mark signal to the second processing module and stores to the first memory a first value of the first clock at which the signal was sent. The second processing module stores to the second memory a second value of the second clock at which the signal was received. The first processing module sends a command to the second processing module, wherein said command includes an execution time for a task relative to the first value. The second processing module determines the execution time for said task relative to the second value and executes said task at said execution time.

Abstract: An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.

Abstract: A voltage reducing circuit comprises a power switch circuit portion comprising a high-side and low-side field-effect-transistors connected at a switch node. The power switch circuit portion has an on-state wherein the high-side transistor is enabled and the low-side transistor is disabled and, vice versa, an off-state. An energy storage circuit portion comprising an inductor connected to the switch node is arranged to provide an output voltage. A drive circuit portion receives a pulse width modulation control signal and outputs pulse width modulated (PWM) drive signals. A pre-biasing circuit portion applies bias voltages to the gate terminals of the high-side and low-side transistors in response to the PWM drive signals, wherein the pre-biasing circuit portion is arranged such that the bias voltage applied to the gate terminal of the currently disabled transistor is set to an intermediate voltage before switching between the on-state and off-state.

Abstract: A radio receiver device, arranged to receive a radio signal modulated with a plurality of data symbols, comprises an analogue-to-digital converter that is clocked by a first clock signal and is arranged to receive the radio signal and produce a digital signal. A digital circuit portion, arranged to receive the digital signal produced by the analogue-to-digital converter, comprises digital processing units that are clocked by a second clock derived from the first clock and arranged to process the digital signal and produce an output signal at an output sample rate. A counter, clocked by the second clock, counts a number of samples at the output sample rate. A network timer clocked by a reference of a network clock produces a receiver enable flag which is synchronised to the first clock. The counter is enabled only when the synchronised flag is set. The counter is arranged to set a trigger flag when the number of samples exceeds a predetermined threshold.

Abstract: A circuit portion for indicating a mutual capacitance between a first and second node is provided. The circuit portion comprises a switchable constant current source arrangement configured to supply a first current to the first node in a first direction or a second current to the first node in a second, opposite direction; a variable voltage source configured to output a voltage to the second node so as to hold the first node at a reference voltage; and a comparator arrangement configured to switch between said first and second directions of the constant current source when the voltage output by the variable voltage source reaches a lower threshold voltage or an upper threshold voltage and to output a signal in synchrony with said constant current direction switching. The signal is indicative of the mutual capacitance between the first and second nodes.

Abstract: An integrated-circuit device includes a bus system, a plurality of master components, a plurality of slave components, and hardware filter logic. The bus system is configured to carry bus transactions and security-state signals for distinguishing between secure and non-secure transactions. The master components are switchable between a secure and a non-secure state. The hardware filter logic is configured to intercept bus transactions at an interception point, positioned within the bus system such that bus transactions from at least two of the master components and at least two slave components pass the interception point. It is also configured to use i) a slave address of the intercepted bus transaction, and ii) the security state of the intercepted bus transaction, to determine whether to allow the transaction, in accordance with a set of filtering rules, and to block intercepted bus transaction that are determined not to be allowed.

Abstract: An electronic device is arranged to receive near-field communication signals and comprises: first and second antenna connection terminals and a variable shunt resistance connected between the first and second antenna connection terminals. The device further comprises a peak detector arranged to detect an amplitude of an incoming near-field communication signal across the antenna connection terminals and to produce a peak signal (Vpd) dependent on the amplitude and a comparator arranged to produce an error signal, wherein the error signal is dependent on a difference between the peak signal and a reference signal (Vrefpeak). The device also comprises an integral controller which is arranged to vary the shunt resistance in response to an integral of the error signal. Said configuration is employed for regulating the received voltage and reducing voltage swing.

Abstract: A radio frequency receiver is provided that comprises an antenna, an RF amplifier, at least one down conversion mixer stage and a variable notch filter. The at least one down-conversion mixer stage is arranged to act on signals provided by the RF amplifier and is tuned to a tuned frequency ft which is selected from a plurality of possible tuned frequencies corresponding to a frequency of the RF signal to be received at the antenna. The variable notch filter is arranged to act on signals passing from the antenna to the RF amplifier and has a resonance frequency fr which is selected from a plurality of possible resonance frequencies such that fr=ft in where n is a whole number between 2 and 10. The variable notch filter thereby acts to attenuate signals from the antenna at said resonance frequency.

Abstract: A signal estimator for an OFDM radio receiver is configured to generate a signal power estimate for a reference signal received on a subcarrier from a plurality of OFDM subcarriers. The signal estimator generates a first channel estimate as a first function of a first set of one or more unfiltered reference-signal channel estimates, where the first set includes an unfiltered reference-signal channel estimate. It generates a second channel estimate as a second function of a second set of one or more unfiltered reference-signal channel estimates, where the second set has no unfiltered reference-signal channel estimate in common with the first set. The signal estimator then generates the signal power estimate by multiplying the first channel estimate with the second channel estimate, such that the generated signal power estimate does not increase with the absolute square of any of the unfiltered reference-signal channel estimates in the first and second sets.

Abstract: An electronic device comprises a first processor and a second processor. An interprocessor communication module is connected to the processors and comprises a high priority mailbox and a low priority mailbox. The first processor sends a high or low priority message to the second processor. The first processor is arranged such that if it has a high priority message to send to the second processor, the first processor places the high priority message in the high priority mailbox and sends an interrupt request to the second processor. However, when the first processor has a low priority message to send to the second processor, the first processor places the high priority message in the low priority mailbox to be checked later without sending an interrupt request to the second processor.

Abstract: A radio receiver is arranged to receive radio signals. The radio receiver includes a tuner, which outputs an electronic signal representing radio waves received by the radio receiver; a correlator, which cross-correlates a predetermined signal pattern with the electronic signal, and outputs a correlation signal; and a clear channel assessment module. The clear channel assessment module determines when the number of peaks in the correlation signal, over a fixed time window, exceeds a threshold count value, and outputs a busy signal in response to determining that the number of peaks exceeds the threshold count value.