Abstract: A method of operating a radio receiver device to monitor a paging group over a paging period. The paging group comprises one or more paging candidates, each having a respective repetition length. The method comprises: receiving one or more data symbols; attempting to decode said received data symbols, wherein a successful decoding attempt produces a decoded message comprising a value indicative of a respective repetition length of said decoded message; and, if the decoding attempt is successful, stopping monitoring of a paging candidate having a respective repetition length greater than said value before the end of the paging period.

Abstract: A radio device sends a random-access request message to a base station and receives a random-access response message from the base station. A plurality of data transport blocks are thereafter transmitted in a first direction between the radio device and the base station, but the radio device does not send a connection-setup complete message to the base station until all of the plurality of data transport blocks having been transmitted.

Abstract: A method of operating a radio receiver having a normal mode in which said radio receiver is arranged to seek information by continually monitoring search space candidates and a rejection mode in which said radio receiver stops monitoring one or more of the candidates.

Abstract: A low noise amplifier comprising a first transconductance amplifier arranged to receive an input voltage at its input terminal and to generate an output current at its output terminal. A second transconductance amplifier is arranged such that its input terminal is connected to the input terminal of the first transconductance amplifier, and such that the output terminal of the second transconductance amplifier is connected to the input terminal of the second transconductance amplifier via a capacitive feedback network (C1).

Abstract: A frequency synthesiser arrangement is arranged to receive a clock input signal and provide an output signal. The frequency synthesiser arrangement comprises: a frequency divider arranged to divide the output signal by a variable number N and output a feedback signal; a phase detector arranged to detect a phase difference between the feedback signal and the clock input signal; a phase alignment circuit portion arranged to determine an overlap of the clock input signal and the feedback signal; and a voltage controlled oscillator which is arranged to receive either a first input derived from the phase detector or a second input from an external reference voltage and to provide the output signal. The phase alignment circuit portion is arranged to provide a control output which determines whether the voltage controlled oscillator receives the first or second input.

Abstract: A processing system is configured to process instructions in a delta file, received at an input of the processing system, to generate a target file from a source file and to regenerate the source file from the target file. The delta file comprises copy instructions and reversing data. The copy instructions instruct the processing system to include one or more copy strings from the source file in the target file. The reversing data is received as part of the delta file and is used to regenerate all of the source file that is outside the one or more copy strings. The processing system is configured to generate the target file from the source file by reading the copy strings from the source file and including them in the target file.

Abstract: An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response. The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.

Abstract: A radio transceiver comprises one or more hardware resources, e.g. a processor; memory; a peripheral device; an algorithmic hardware accelerator; and/or a radio frequency component. A cellular communication radio is operable in an active mode in which it has access to the one or more hardware resources for transmitting and/or receiving cellular communication signals, and an inactive mode in which it does not. A global navigation satellite systems radio, arranged to use the one or more hardware resources to receive positioning signals, has access to the one or more hardware resources only when the cellular communication radio is operated in the inactive mode.

Abstract: A digital radio receiver has a matched filter bank of filter modules for receiving phase- or frequency-modulated radio signals. Each module cross-correlates a sampled signal with a respective multi-symbol filter sequence, using a plurality of samples in each symbol period. The matched filter bank calculates first values (zn(1)), for respective symbol periods, of a cross-correlation of the sampled signal with a first complex exponential function defined at sample points over one symbol period, and calculates second values (zn(?1)), for the respective symbol periods, of a cross-correlation of the sampled signal with a second, different, complex exponential function.

Abstract: An electronic device comprises a first circuit portion comprising one or more components, including a first counter, which are clocked by a first clock signal. The first circuit portion is arranged to receive a data stream comprising a plurality of data signals. A second circuit portion comprises one or more components clocked by a second clock signal and a second counter not clocked by the second clock signal. The first clock signal is not synchronised to the second clock signal. The second circuit portion is arranged to: receive samples of the data stream from the first circuit portion at a sample rate and to time-stamp each received sample with a count value of the second counter. The second circuit portion increments the count value of the second counter by a predetermined increment value for each received sample.

Abstract: In an aspect, a wireless communication between a transmitter and a receiver involves determining updated keys according to a key management process for MAC layer encryption. Such key is propagated to a transmitter MAC and though a receiver key management process to a receiver MAC. After a delay, transmitter MAC device begins using the updated key, instead of a prior key, for payload encryption. Receiver MAC continues to use the prior key until a packet that was accurately received fails a message integrity/authentication check. Then, the receiver MAC swaps in the updated key and continues to process received packets. The packet data that failed the message integrity check is discarded. Transmitter MAC retries the failed packet at a later time, and if the packet was accurately received and was encrypted by the transmitter MAC using the updated key, then the receiver will determine that the message is authentic and will receive it and acknowledge it.

Abstract: A digital radio communication system comprises a central device and a peripheral device arranged to operate in accordance with a predetermined communication protocol. The central and peripheral devices are both arranged to: transmit data packets over a plurality of available radio channels having different frequencies; receive the data packets transmitted by the other respective device; and perform data integrity checks on the data packets received. At least one of the central and peripheral devices is arranged to assign a dynamic channel rating to one or more of said radio channels based on an outcome of at least some of the data integrity checks.

Abstract: A voltage monitoring circuit portion is arranged to monitor a negative supply voltage (Vneg) and comprises a negative voltage generator arranged to generate the negative supply voltage (Vneg) and to output the negative supply voltage (Vneg) at an output terminal. A capacitor is arranged so that a first capacitor plate is connected to the output terminal of the generator and to a reference node via a potential divider. The potential divider is arranged to produce a monitor voltage (Vmonitor) between the resistors, where the reference node is supplied with a positive predetermined reference voltage (Vref). A comparator compares the monitor voltage (Vmonitor) to a threshold voltage (Vref_low) and to produce an output signal having a first value when the monitor voltage (Vmonitor) is below the threshold voltage (Vref_low) and having a second value otherwise. The negative voltage generator is enabled only when the output signal has its second value.

Abstract: A voltage divider circuit arrangement includes a resistive divider circuit portion constructed from first and second resistors (R1, R2) The first and second resistors are connected in series and are arranged to provide a refresh voltage (Vrefresh) at a refresh node between them. A capacitive divider circuit portion is constructed from first and second capacitors (C1, C2). The first and second capacitors are connected in series and are arranged to provide an output voltage (Vout) at an output node. A switching circuit portion is arranged intermittently to switch the voltage divider circuit arrangement between a first mode wherein the resistive divider is enabled and the output node is connected to the refresh node, and a second mode wherein the resistive divider is disabled and the output node is not connected to the refresh node.

Abstract: A method of communication over a cellular telecommunications network using an electronic device comprises communicating a session control signal between the electronic device and the cellular telecommunications network on a first radio channel provided by the cellular telecommunications network. The session control signal comprises identification data that identifies a remote party. The cellular telecommunications network uses the identification data to establish an IP-based communication session with the remote party. Content data for the IP-based communication session is communicated between the electronic device and the cellular telecommunications network on a second radio channel provided by the cellular telecommunications network.

Abstract: An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.

Abstract: An integrated circuit device has a processor, a software-trace message handling system, a software-trace message sink peripheral, and a hardware interconnect system. The interconnect system is capable of directing software-trace messages from the processor to the software-trace message handling system, and of directing software-trace messages from the processor to the software-trace message sink peripheral. The software-trace message sink peripheral can present an interconnect delay to the processor, when receiving a software-trace message from the processor, that is equal to or substantially equal to an interconnect delay that the software-trace message handling system would have presented to the processor if the software-trace message handling system were to have received the software-trace message.

Abstract: A radio receiver is provided for low-power detection of a radio signal, wherein said receiver is configured to receive a radio signal over a radio network; convert at least part of the received radio signal into a sequence of samples; compare the similarity of a first part of the sequence and a second part of the sequence, wherein the first part and the second part are of equal length; and in response to said similarity being greater than a similarity threshold: detect a phase difference between the first part of the sequence and the second part of the sequence; calculate a frequency offset between a frequency of the received radio signal and an expected frequency of the received radio signal using said phase difference; and use said calculated frequency offset to attempt full access to the radio network.

Abstract: A radio receiver of a radio communication system is configured to tune to a radio channel by generating a periodic signal, mixing the periodic signal with radio signals received from a radio transmission system and passing the mixed signal through a channel filter. The radio receiver receives, from the radio transmission system, an OFDM data signal modulated on a set of OFDM subcarriers within the tuned channel. The channel filter has a passband that is wider than the channel bandwidth of the tuned channel such that the filter passes i) said OFDM data signal, ii) an in-channel reference signal, and iii) an out-of-channel reference signal. The radio receiver comprises channel estimation logic configured to use both reference signals to calculate a channel estimate for an OFDM subcarrier within the tuned channel.

Abstract: An integrated-circuit device comprises first and second peripherals, connected to a processor via a bus system, a peripheral interconnect that is separate from the bus system, wake up logic, a configuration memory and a power controller. In response to a change of state, the first peripheral generates event signals that are output to the peripheral interconnect. The peripheral interconnect provides the event signal to the second peripheral, which initiates tasks in response, The first peripheral, second peripheral and the wake-up logic are in a first, second and third power domain respectively. The power controller provides power to the third power domain whenever the first or second power domain is powered up. The wake-up logic detects an event signal from the first peripheral and, if it determines that the second peripheral is configured to initiate a task in response, it instructs the power controller to power up the second peripheral.