Abstract: A hardware cipher engine encrypts or decrypts a block of input data from a sequence of blocks using a cipher operation where the block of output data depends on the input block's position in the sequence. In a random-access mode of operation, the engine receives a sequence position, receives a block of input data having that position, and outputs a block of output data without outputting data that encrypts, or that decrypts, every block of input data preceding the received position. In some embodiments, the operation is a stream cipher, and the engine generates a sequence of keystream blocks and performs a combining operation between the input block and a keystream block having a corresponding sequence position. In other embodiments, the cipher operation is a block cipher, and the engine generates, but doesn't output, blocks of data that encrypt, or decrypt, one or more blocks preceding the received input block.

Abstract: A method of communication over a cellular telecommunications network using an electronic device comprises communicating a session control signal between the electronic device and the cellular telecommunications network on a first radio channel provided by the cellular telecommunications network. The session control signal comprises identification data that identifies a remote party. The cellular telecommunications network uses the identification data to establish an IP-based communication session with the remote party. Content data for the IP-based communication session is communicated between the electronic device and the cellular telecommunications network on a second radio channel provided by the cellular telecommunications network.

Abstract: A method for analyzing a frequency stability of a radio transceiver device comprises receiving a first succession of unmodulated radio-frequency signals of different frequencies from a radio transceiver apparatus. For each unmodulated radio-frequency signal, a respective time series of phase-offset values is determined, each phase-offset value being representative of a difference between a phase of the respective received unmodulated radio-frequency signal and a phase of a respective reference signal. The time series of phase-offset values is processed to determine a respective signal-phase-offset value for each unmodulated radio-frequency signal. A frequency-stability value, representative of a frequency stability of the radio transceiver apparatus, is calculated as a function representative of statistical variation in the signal-phase-offset values determined for the first succession of unmodulated radio-frequency signals.

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract: An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.

Abstract: An apparatus has a radio for communicating with LTE networks using a first access technology and for communicating with LTE networks using a second access technology. The apparatus is configured to access an identity-data memory storing received identity data. The apparatus includes an access-technology-identification memory for storing access-technology identification information that identifies an access technology associated with identity data stored in the identity-data memory. The apparatus registers with an LTE cellular network, using a selected access technology. The apparatus processes the access-technology identification information to determine whether the identity data stored in the identity-data memory is associated with the selected access technology, and, when it is associated, sends the identity data to the LTE network.

Abstract: An integrated-circuit device includes a bus system, a plurality of master components, a plurality of slave components, and hardware filter logic. The bus system is configured to carry bus transactions and security-state signals for distinguishing between secure and non-secure transactions. The master components are switchable between a secure and a non-secure state. The hardware filter logic is configured to intercept bus transactions at an interception point, positioned within the bus system such that bus transactions from at least two of the master components and at least two slave components pass the interception point. It is also configured to use i) a slave address of the intercepted bus transaction, and ii) the security state of the intercepted bus transaction, to determine whether to allow the transaction, in accordance with a set of filtering rules, and to block intercepted bus transaction that are determined not to be allowed.

Abstract: A method of determining a distance between a radio frequency device and a target is disclosed in which the radio frequency device receives a radio frequency signal from the target. The method comprises determining a time domain channel response from the received radio frequency signal, determining an amplitude of a largest peak in the time domain channel response, determining an amplitude of a second, earlier, peak in the time domain channel response, comparing the second peak amplitude to a threshold based on the largest peak amplitude, identifying the largest peak as a shortest path peak if the second peak amplitude is less than the threshold, identifying the second peak as a shortest path peak if the second peak amplitude is greater than the threshold, and calculating the distance between the radio frequency device and the target based on a time corresponding to the shortest path peak.

Abstract: A method of digital radio communication between a first device and a second device is disclosed. An advertising packet is transmitted between first and second devices, wherein the packet includes a first address and a data portion. Additionally, an encryption key is transmitted between the devices. The first device generates a second address by encrypting an identity value derived from part of the first address using the encryption key and the data portion. The result is encrypted to generate second portion of the second address. The first device then transmits a connection request including the second address. The second device decrypts the second portion and uses the encryption key to determine correspondence with the first portion. If said correspondence is determined, the second device decrypts the first portion using at least the encryption key and compares it to an expected identity value derived from the first address.

Abstract: A method for determining a distance between an initiator radio transceiver and a reflector radio transceiver is provided. The method comprises the initiator radio transceiver transmitting a first radio signal at a first transmission time and the reflector radio transceiver receiving the first radio signal at a first reception time. The reflector transceiver samples the first radio signal using a sampling clock signal having a sampling period and determines a first reception-time value at a temporal resolution that is finer than the sampling period, including a fractional component representative of a fraction of the sampling period. The reflector transceiver transmits a second radio signal at a second transmission time that is offset from the sampling clock signal by an amount that depends on said fractional component so as to provide a predetermined dwell time that is determined to an accuracy finer than the sampling period.

Abstract: A computer system configured to enable communication between two or more virtual platforms is disclosed. The computer system comprises a physical processor configured to run the two or more virtual platforms. The computer system further comprises a memory. The memory comprises one or more separate memory portions allocated to each of the two or more virtual platforms, wherein within at least one memory portion allocated to one of the virtual platform a predefined range of addresses is configured as a shared device memory, the shared device memory being accessible by all the virtual platforms. Firmware running on a first virtual platform is configured to transfer a data packet from the first virtual platform to one or more further virtual platforms via the shared device memory.

Abstract: An oscillator circuit comprises a crystal oscillator and an inverter. The input of the inverter is connected to the first terminal of the crystal oscillator and the output of the inverter is connected to the second terminal of the crystal oscillator, oscillator circuit is arranged to operate the inverter in its linear operating region. An amplitude regulator has an input connected to the input of the inverter, arranged to provide a first supply current IAREG to the inverter, where the magnitude of the first supply current is inversely dependent on a magnitude of a voltage at the inverter input. A digital-to-analogue converter is arranged to provide a second supply current IDAC to the inverter having a magnitude determined by a digital signal applied to a digital input of the digital-to-analogue converter.

Abstract: A circuit portion for indicating a mutual capacitance between a first and second node is provided. The circuit portion comprises a switchable constant current source arrangement configured to supply a first current to the first node in a first direction or a second current to the first node in a second, opposite direction; a variable voltage source configured to output a voltage to the second node so as to hold the first node at a reference voltage; and a comparator arrangement configured to switch between said first and second directions of the constant current source when the voltage output by the variable voltage source reaches a lower threshold voltage or an upper threshold voltage and to output a signal in synchrony with said constant current direction switching. The signal is indicative of the mutual capacitance between the first and second nodes.

Abstract: A method of transferring data from a first bus to a second bus across an asynchronous interface using an asynchronous bridge. The bridge comprises a bus slave module, connected to the first bus, comprising a forward-channel initiator in a first power and/or clock domain; and a bus master module, connected to the second bus, comprising a forward-channel terminator in a second power and/or clock domain. The forward-channel initiator and terminator are in communication to form a forward lockable mutex for arbitrating access to signals used to transfer data from the first domain to the second domain. If the mutex is locked, a forward data channel is used to transfer data between the domains. Otherwise if the mutex is unlocked, the forward channel initiator toggles a status request signal and the forward channel terminator toggles a status acknowledge signal in response, the mutex thereby becoming locked.

Abstract: A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to each load for one or more discrete time slots. The number of time slots is greater than the number of loads so that at least two output loads receive current for different numbers of time slots in a cycle.

Abstract: A circuit portion comprises a DCDC converter that is configured to charge and discharge an inductor according to a duty cycle to provide current to an output load. A duty module is configured to determine the duty cycle such that the DCDC converter will output a target current. A duty limiter module is configured to cause the inductor to discharge early if the determined duty cycle exceeds a threshold.

Abstract: An integrated circuit system comprises first and second processing modules. The first processing module comprises a first processor, clock and memory; and the second processing module comprises a second processor, clock and memory. The first processing module sends a time-mark signal to the second processing module and stores to the first memory a first value of the first clock at which the signal was sent. The second processing module stores to the second memory a second value of the second clock at which the signal was received. The first processing module sends a command to the second processing module, wherein said command includes an execution time for a task relative to the first value. The second processing module determines the execution time for said task relative to the second value and executes said task at said execution time.

Abstract: Methods for logging strings during execution of a program running on an embedded system without storing the strings in the memory of the embedded system include, during the build process, receiving source code for a program that comprises one or more log statements that identifies a string to be logged; generating object code based on the source code that comprises a special log section that includes the identified strings, and, for each log statement one or more instructions that cause a reference to the corresponding string to be stored in memory of the embedded system; generating execution code based on the object code wherein the special log section is marked as non-loadable and each reference is a location of the corresponding string in the special log section; and, loading the generated executable code into the memory of the embedded system such that the identified strings are not loaded into the memory of the embedded system.

Abstract: A demodulator for a digital radio receiver comprises a frequency discriminator and a Viterbi decoder. The frequency discriminator receives a series digital signal samples representative of an FSK-modulated signal and performs frequency discrimination on the digital signal samples to generate a series of frequency samples. Each frequency sample represents an instantaneous frequency of the signal in a respective frequency-sample period. There are an integer oversampling factor, N>1, of frequency-sample periods in each symbol period. The Viterbi decoder receives the series of frequency samples, determines branch metrics for each symbol period by determining distances between a vector of N successive frequency samples and each of a plurality of reference waveform vectors, each comprising N elements. It use the branch metrics in a Viterbi process to output demodulated symbol values corresponding to a maximum-likelihood decoding of the FSK-modulated signal.

Abstract: A radio device receives data from a base station that transmits a first radio signal, carrying a first data block, in a first time window, and a second radio signal, also carrying the first data block, in a different, second time window. The radio device comprises first and second antennas, receive circuitry, and a switch for selectively connecting the receive circuitry to the first antenna or to the second antenna. It is configured to sample the first radio signal, received by the first antenna in the first time window, to generate first sampled data; disconnect the first antenna from the receive circuitry and connect the second antenna; sample the second radio signal, received by the second antenna in the second time window, to generate second sampled data; and use both the first sampled data and the second sampled data to decode the first data block.