Abstract: A radio receiver of a radio communication system is configured to tune to a radio channel by generating a periodic signal, mixing the periodic signal with radio signals received from a radio transmission system and passing the mixed signal through a channel filter. The radio receiver receives, from the radio transmission system, an OFDM data signal modulated on a set of OFDM subcarriers within the tuned channel. The channel filter has a passband that is wider than the channel bandwidth of the tuned channel such that the filter passes i) said OFDM data signal, ii) an in-channel reference signal, and iii) an out-of-channel reference signal. The radio receiver comprises channel estimation logic configured to use both reference signals to calculate a channel estimate for an OFDM subcarrier within the tuned channel.

Abstract: A semiconductor integrated-circuit device comprises two processing subsystems, each comprising a respective processor, set of local peripherals, and bridge unit, all connected to a respective local bus. An electrical interconnect joins the respective bridge units. The first bridge unit comprises a task register, accessible over the first local bus, and can be configured to detect a write to the task register, and respond by sending an event signal over the interconnect to the second bridge unit. The second bridge unit can be configured to receive the event signal, and respond by sending an interrupt signal to the second processor.

Abstract: A cryptographic module is switchable between a key-input mode and a data-input mode. In the key-input mode, the cryptographic module receives key data, key length information and first input data, combines an amount of the key data corresponding to the key length information with the first input data to produce combined data, wherein a key-influenced length of the combined data is the shortest length of the combined data that contains every data bit of the combined data whose value depends on the key data. It performs a cryptographic operation on the combined data to generate first output data and does not output any of the first output data until after the cryptographic operation has been applied to all of the key-influenced length of the combined data.

Abstract: A radio receiver device is arranged to store samples of incoming data symbols in an indexed memory portion having a length of A+B+C. A first data buffer 20-1 has an initial address at index 0 and a final address at index A-1. A timing adjustment buffer 22 has an initial address at index A and a final address at index A+B?1. A second data buffer 20-2 has an initial address at an index A+B and a final address at an index A+B+C?1. A buffer switch pointer 24 has a trigger address between the index 0 and the index A+B?1, at which it triggers a switch 26 from the first to the second buffer. If the current address matches the trigger address, the current address is set to the index A+B. Otherwise, the current address is incremented. If there is a timing offset between local and network clocks, the trigger address is moved to reduce the offset.

Abstract: An electronic device comprises a first processor and a second processor. An inter-processor communication module is connected to the processors and comprises a high priority mailbox and a low priority mailbox. The first processor sends a high or low priority message to the second processor. The first processor is arranged such that if it has a high priority message to send to the second processor, the first processor places the high priority message in the high priority mailbox and sends an interrupt request to the second processor. However, when the first processor has a low priority message to send to the second processor, the first processor places the high priority message in the low priority mailbox to be checked later without sending an interrupt request to the second processor.

Abstract: A microcontroller system comprising a master microcontroller unit, a further module and a general purpose input/output. In a first state the general purpose input/output is controlled by the master microcontroller unit and in a second state the general purpose input/output is controlled by the further module. The master microcontroller unit is arranged to transmit a selection signal which changes the state of the general purpose input/output.

Abstract: A device comprising: a transceiver operable in a first or second mode and configured to receive packets from a remote device, each packet comprising an indication of whether or not the remote device has a further packet to transmit, wherein: in the first mode the transceiver: (i) sends a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for that further packet; and in the second mode the transceiver: (i) does not send a polling message in response to receiving the indication of a further packet for transmission; and (ii) listens for packets regardless of whether a received packet indicates that there is a further packet to transmit or not; and a controller configured to monitor an activity level for the transceiver and cause the transceiver to operate in the first or second mode in dependence on the activity level.

Abstract: A digital radio receiver receives an encoded digital radio signal comprising a plurality of bits. The receiver determines a plurality of soft bits representing estimates of the bits and stores the soft bits in a rate de-matching buffer. The receiver calculates a first linear combination of soft bits from a first subset of the buffer and a second linear combination of soft bits from a second subset of the buffer. The receiver calculates a ratio between the first and second linear combinations and compares the ratio to an expected value. The receiver then determines its operational state based on the comparison.

Abstract: A method of encoding a variable, which may have a plurality of different states, using an integrated circuit comprising a physical unclonable function module. The method comprises using the physical unclonable function module to generate a fingerprint value deterministically dependent on one or more physical fabrication properties of the integrated circuit; generating a first encoding value using the fingerprint value; generating a second encoding value using the fingerprint value; and encoding said variable using said encoding values.

Abstract: A method of operating a radio receiver arranged to receive a plurality of data symbols transmitted on one of a predetermined set of frequencies. The method comprises receiving a first set of data symbols at a first transmission frequency. The first set of data symbols comprises a message indicating a first frequency sub-set. A synthesiser is calibrated for the one or more frequencies in the first frequency sub-set. A second set of data symbols transmitted on at least one of said one or more frequencies from the first sub-set is received. It is determined from the second set of data symbols whether a network quality metric exceeds a threshold. The synthesiser is calibrated for one or more frequencies in a second frequency sub-set when the network quality metric exceeds the threshold. The second sub-set comprises frequencies that are not in the first sub-set.

Abstract: A radio receiver apparatus comprises radio circuitry for receiving a sequence of radio data packets, transmitted at regular intervals, wherein the sequence of radio data packets encodes a digital audio stream and each radio data packet encodes a respective number of audio samples from the digital audio stream. The apparatus also comprises a digital audio interface for outputting audio samples from the received digital audio stream, a controllable oscillator arranged to control an output rate at which the audio samples are output from the digital audio interface, and a timer. The apparatus also comprises control logic, configured to use the timer to measure an interval between receiving each of a pair of the radio data packets, and to control the oscillator to vary the output rate incrementally, in a number of steps, while outputting the audio samples from one radio data packet. The number of steps, or the size of each step, or both, depends on the measured interval.

Abstract: A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

Abstract: A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

Abstract: A circuit system comprises a processor, a first clock with a first frequency, a second clock with a second frequency, such second frequency being higher than said first frequency and a clock calibration module. The clock calibration module comprises a plurality of counters configured to count cycles of the second clock when triggered. Each of the plurality of counters is configured to be triggered at successive cycles of the first clock. Each of the plurality of counters is configured, after a predetermined number of cycles of the first clock, to output a count of elapsed second clock cycles and the processor is configured to determine, using the counts outputted by the plurality of counters, a ratio between the first frequency and the second frequency.

Abstract: Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P?PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.

Abstract: An electronic device comprises a processor operable at a variable processor privilege level and a memory comprising a secure memory area. A hardware module is operable at a variable module privilege level and is arranged to access the memory directly. The secure memory area is accessible by the hardware module only when the module privilege level exceeds a threshold value. The device has a first mode of operation in which said processor privilege level is higher than said threshold value and said module privilege level is lower than said threshold value. A controller is arranged, upon receiving a privilege promotion signal and the device being in the first mode, to move the device to a second mode wherein the module privilege level is higher than said threshold value.

Abstract: A radio transceiver device comprises a transmit amplifier, a receive amplifier, an impedance matching circuit portion, and an antenna connection node for connection to an antenna. The impedance matching circuit portion is arranged between the antenna connection node and each of the transmit and receive amplifiers. The impedance matching circuit portion comprises a switch and an inductor and is arranged such that, in a receive mode of operation, the switch is first state and incoming signals from the antenna pass to the receive amplifier via the inductor. In a transmit mode of operation, the switch is in a second state and the transmit amplifier is coupled to a power supply rail VDD via the inductor.

Abstract: A radio system comprises a radio transmitter apparatus and a radio receiver apparatus. The radio transmitter apparatus is configured to transmit a continuous-wave radio-frequency signal having a first frequency. The radio receiver apparatus comprises: an antenna for receiving the continuous-wave radio-frequency signal; a local oscillator for generating a periodic signal at a second frequency which differs from the first frequency by a frequency offset; a mixer for mixing the received continuous-wave radio-frequency signal with the periodic signal to generate a down-mixed signal; and a processor or other circuitry configured to generate frequency-offset data from the down-mixed signal, wherein the frequency-offset data is representative of an estimate of the frequency offset. The processor or other circuitry is configured to use the frequency-offset data to generate DC-offset data representative of an estimate of a DC offset component of the down-mixed signal.

Abstract: A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.

Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.