Patents Assigned to Novellus Systems, Inc.
  • Patent number: 9121097
    Abstract: Apparatuses and techniques for providing for variable radial flow conductance within a semiconductor processing showerhead are provided. In some cases, the radial flow conductance may be varied dynamically during use. In some cases, the radial flow conductance may be fixed but may vary as a function of radial distance from the showerhead centerline. Both single plenum and dual plenum showerheads are discussed.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 1, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Mohn, Shawn M. Hamilton, Harald te Nijenhuis, Jeffrey E. Lorelli, Kevin Madrigal
  • Patent number: 9117668
    Abstract: Smooth silicon films having low compressive stress and smooth tensile silicon films are deposited by plasma enhanced chemical vapor deposition (PECVD) using a process gas comprising a silicon-containing precursor (e.g., silane), argon, and a second gas, such as helium, hydrogen, or a combination of helium and hydrogen. Doped smooth silicon films and smooth silicon germanium films can be obtained by adding a source of dopant or a germanium-containing precursor to the process gas. In some embodiments dual frequency plasma comprising high frequency (HF) and low frequency (LF) components is used during deposition, resulting in improved film roughness. The films are characterized by roughness (Ra) of less than about 7 ?, such as less than about 5 ? as measured by atomic force microscopy (AFM), and a compressive stress of less than about 500 MPa in absolute value. In some embodiments smooth tensile silicon films are obtained.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: August 25, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Alice Hollister, Sirish Reddy, Keith Fox, Mandyam Sriram, Joe Womack
  • Patent number: 9117884
    Abstract: A layer of diffusion barrier or seed material is deposited on a semiconductor substrate having a recessed feature. The method may include a series of new deposition cycles, for example, a first net deposition cycle and a second net deposition cycle. The first net deposition cycle includes depositing a first deposited amount of the diffusion barrier or seed material and etching a first etched amount of the diffusion barrier or seed material. The second net deposition cycle including depositing a second deposited amount of the diffusion barrier or seed material and etching a second etched amount of the diffusion barrier or seed material. At least one of the process parameters of the first cycle differs from that of the second allows providing a graded deposition effects to reduce a risk of damaging any under layers and dielectric. A deposited layer of diffusion barrier or seed material is generally more conformal.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 25, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Roey Shaviv, Sanjay Gopinath, Peter Holverson, Anshu A. Pradhan
  • Patent number: 9109295
    Abstract: An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: August 18, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Seshasayee Varadarajan, Steven T. Mayer
  • Patent number: 9111733
    Abstract: A plasma ignition system includes a first voltage supply that selectively supplies a plasma ignition voltage and a plasma maintenance voltage across an adapter ring and a cathode target of a physical vapor deposition (PVD) system. A second voltage supply selectively supplies a second voltage across the adapter ring and an anode ring of the PVD system. A plasma ignition control module ignites plasma using the plasma ignition voltage and the auxiliary plasma ignition voltage and, after the plasma ignites, supplies the plasma maintenance voltage and ceases supplying the plasma ignition voltage and the auxiliary plasma ignition voltage.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: August 18, 2015
    Assignee: Novellus Systems Inc.
    Inventors: Martin Freeborn, Vince Burkhart
  • Patent number: 9099535
    Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: August 4, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Robert Rozbicki, Michal Danek, Erich Klawuhn
  • Patent number: 9088085
    Abstract: Embodiments include a high temperature electrode connection assembly for a wafer-processing pedestal. The high temperature electrode connection assembly includes an electrode rod having a cup that mounts to a stud embedded in the pedestal and a plate adapter portion. The assembly also includes a floating plate having an outer surface and an aperture for receiving the electrode rod. The floating plate contacts an inner surface of the pedestal to resist lateral movement of the electrode rods. The assembly also includes an anti-rotation retainer ring that frictionally engages the electrode rod and an anti-rotation post extending from the outer surface of the floating plate. The anti-rotation post limits rotation of the electrode rod with respect to the floating plate.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 21, 2015
    Assignee: Novellus Systems, Inc.
    Inventor: Gary Lind
  • Patent number: 9082589
    Abstract: In one aspect, a system includes a generator configured to generate and tune a frequency of a supply signal. The system includes an auto-matching network configured to receive the supply signal and to generate an impedance-matched signal for use in powering a plasma system. In some implementations, during a first stage of an impedance matching operation, the generator is configured to tune the frequency of the supply signal until the generator identifies a frequency for which the reactance of the generator and the reactance of the load are best matched. In some implementations, during a second stage of the impedance matching operation, the auto-matching network is configured to tune a tuning element within the auto-matching network until the auto-matching network identifies a tuning of the tuning element for which the resistance of the generator and the resistance of the load are best matched.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: July 14, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: George Thomas, Panya Wongsenakhum, Francisco J. Juarez
  • Patent number: 9076843
    Abstract: A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: July 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Sang-Hyeob Lee, Joshua Collins
  • Patent number: 9073100
    Abstract: Porogen accumulation in a UV-cure chamber is reduced by removing outgassed porogen through a heated outlet while purge gas is flowed across a window through which a wafer is exposed to UV light. A purge ring having specific major and minor exhaust to inlet area ratios may be partially made of flame polished quartz to improve flow dynamics. The reduction in porogen accumulation allows more wafers to be processed between chamber cleans, thus improving throughput and cost.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: July 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Lisa Gytri, Jeff Gordon, James Lee, Carmen Balderrama, Joseph Brett Harris, Eugene Smargiassi, Stephen Yu-Hong Lau, George D. Kamian, Ming Xi
  • Patent number: 9074287
    Abstract: Methods and apparatus for isotropically etching a metal from a work piece, while recovering and reconstituting the chemical etchant are described. Various embodiments include apparatus and methods for etching where the recovered and reconstituted etchant is reused in a continuous loop recirculation scheme. Steady state conditions can be achieved where these processes are repeated over and over with occasional bleed and feed to replenish reagents and/or adjust parameters such as pH, ionic strength, salinity and the like.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter
  • Patent number: 9074286
    Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 7, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Eric Webb, David W. Porter
  • Patent number: 9070555
    Abstract: Described are methods of making silicon nitride (SiN) materials on substrates. Improved SiN films made by the methods are also included. One aspect relates to depositing chlorine (Cl)-free conformal SiN films. In some embodiments, the SiN films are Cl-free and carbon (C)-free. Another aspect relates to methods of tuning the stress and/or wet etch rate of conformal SiN films. Another aspect relates to low-temperature methods of depositing high quality conformal SiN films. In some embodiments, the methods involve using trisilylamine (TSA) as a silicon-containing precursor.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 30, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Dennis Hausmann, Jon Henri, Bart van Schravendijk, Easwar Srinivasan
  • Patent number: 9070750
    Abstract: Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. Metal oxide surfaces are reduced to form a film integrated with a metal seed layer on a substrate by exposing the metal oxide surfaces to a reducing gas atmosphere comprising radicals of a reducing gas species. The radicals of the reducing gas species can form from exposing the reducing gas species to ultraviolet radiation and/or a plasma. The substrate is maintained at a temperature below a temperature that produces agglomeration of the metal seed layer during exposure to the reducing gas atmosphere, such as below 150° C. for copper. In some embodiments, the reducing gas species can include at least one of hydrogen, ammonia, carbon monoxide, diborane, sulfite compounds, carbon and/or hydrocarbons, phosphites, and hydrazine.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: June 30, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Tighe A. Spurlin, Darcy E. Lambert, Durgalakshmi Singhal, George Andrew Antonelli
  • Patent number: 9064684
    Abstract: Methods and apparatus for filling gaps on partially manufactured semiconductor substrates with dielectric material are provided. In certain embodiments, the methods include introducing a first process gas into the processing chamber and accumulating a second process gas in an accumulator maintained at a pressure level substantially highest than that of the processing chamber pressure level. The second process gas is then rapidly introduced from the accumulator into the processing chamber. An excess amount of the second process gas may be provided in the processing chamber during the introduction of the second process gas. Flowable silicon-containing films forms on a surface of the substrate to at least partially fill the gaps.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: June 23, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Collin K. L. Mui, Lakshminarayana Nittala, Nerissa Draeger
  • Patent number: 9050623
    Abstract: Porous ULK film is cured with UV radiation at progressively shorter wavelengths to obtain ULK films quickly at a desired dielectric constant with improved mechanical properties. At longer wavelengths above about 220 nm or about 240 nm, porogen is removed while minimizing silicon-carbon bond formation. At shorter wavelengths, mechanical properties are improved while dielectric constant increases.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 9, 2015
    Assignee: Novellus Systems, Inc.
    Inventor: Bhadri N. Varadarajan
  • Patent number: 9045840
    Abstract: Methods, systems, and apparatus for plating a metal onto a work piece are described. In one aspect, an apparatus includes a plating chamber, a substrate holder, an anode chamber housing an anode, and an ionically resistive ionically permeable element positioned between a substrate and the anode chamber during electroplating. The anode chamber may be movable with respect to the ionically resistive ionically permeable element to vary a distance between the anode chamber and the ionically resistive ionically permeable element during electroplating. The anode chamber may include an insulating shield oriented between the anode and the ionically resistive ionically permeable element, with opening in a central region of the insulating shield.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: June 2, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: David W. Porter, Jonathan D. Reid, Frederick D. Wilmot
  • Patent number: 9045841
    Abstract: In a copper electroplating apparatus having separate anolyte and catholyte portions, the concentration of anolyte components (e.g., acid or copper salt) is controlled by providing a diluent to the recirculating anolyte. The dosing of the diluent can be controlled by the user and can follow a pre-determined schedule. For example, the schedule may specify the diluent dosing parameters, so as to prevent precipitation of copper salt in the anolyte. Thus, precipitation-induced anode passivation can be minimized.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: June 2, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Bryan Buckalew, Jonathan Reid, John Sukamto, Zhian He, Seshasayee Varadarajan, Steven T. Mayer
  • Patent number: 9034773
    Abstract: Provided are methods and systems for removing a native silicon oxide layer on a wafer. In a non-sequential approach, a wafer is provided with a native silicon oxide layer on a polysilicon layer. An etchant including a hydrogen-based species and a fluorine-based species is introduced, exposed to a plasma, and flowed onto the wafer at a relatively low temperature. The wafer is then heated to a slightly elevated temperature to substantially remove the native oxide layer. In a sequential approach, a wafer is provided with a native silicon oxide layer. A first etchant including a hydrogen-based species and a fluorine-based species is flowed onto the wafer. Then the wafer is heated to a slightly elevated temperature, a second etchant is flowed towards the wafer, and the second etchant is exposed to a plasma to complete the removal of the native silicon oxide layer and to initiate removal of another layer such as a polysilicon layer.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Bayu Thedjoisworo, David Cheung, Joon Park
  • Patent number: 9034768
    Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials are provided. The method involves providing a partially fabricated semiconductor substrate and depositing a tungsten-containing layer on the substrate surface to partially fill one or more high aspect ratio features. The method continues with selective removal of a portion of the deposited layer such that more material is removed near the feature opening than inside the feature. In certain embodiments, removal may be performed at mass-transport limited conditions with less etchant available inside the feature than near its opening. Etchant species are activated before being introduced into the processing chamber and/or while inside the chamber. In specific embodiments, recombination of the activated species is substantially limited and/or controlled during removal, e.g., operation is performed at less than about 250° C. and/or less than about 5 Torr.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang