Abstract: The present invention relates to an enhanced cyclic deposition process suitable for deposition of barrier layers, adhesion layers, seed layers, low dielectric constant (low-k) films, high dielectric constant (high-k) films, and other conductive, semi-conductive, and non-conductive films. The deposition enhancement is derived from ions generated in a plasma. The techniques described reduce the time required for plasma stabilization, thereby reducing deposition time and improving efficiency.

Abstract: Disclosed are apparatus and methods for monitoring an operation parameter of a process tool, independently of a process system recipe, are provided. In general, an indirect effect that results from implementing an event from a process system recipe on the process system is monitored without using the specific values or setpoints that are entered for such event into the process system to thereby change a state of such process system. In one embodiment, the behavior of a process device as it transitions between different states is monitored for a single cycle of operation or over time to detect trends that indicate a potential failure of the process device. When a trend that indicates a potential failure is detected, an alarm is generated. In one implementation, the time for reaching a particular stage of operation may be repeatedly monitored over a plurality of device cycles. For example, the time to open a valve or door may be monitored.

Abstract: Methods and apparatuses that decouple wafer temperature from pre-heat station residence time, thereby improving wafer-to-wafer temperature uniformity, are provided. The methods involve maintaining a desired temperature by varying the distance between the wafer and a heater. In certain embodiments, the methods involve rapidly approaching a predetermined initial distance and then obtaining and maintaining a desired final temperature using closed loop temperature control. In certain embodiments, a heated pedestal supplies the heat. The wafer-pedestal gap may be modulated may be varied by moving the heated pedestal and/or moving the wafer, e.g., via a movable wafer support. Also in certain embodiments, the closed loop control system includes a real time wafer temperature sensor and a servo controlled linear motor for moving the pedestal or wafer support.

Abstract: Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.

Abstract: Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.

Abstract: Improved methods for depositing low resistivity tungsten films are provided. The methods involve depositing a tungsten nucleation layer on a substrate and then depositing a tungsten bulk layer over the tungsten nucleation layer to form the tungsten film. The methods provide precise control of the nucleation layer thickness and improved step coverage. According to various embodiments, the methods involve controlling thickness and/or improving step coverage by exposing the substrate to pulse nucleation layer (PNL) cycles at low temperature. Also in some embodiments, the methods may improve resistivity by using a high temperature PNL cycle of a boron-containing species and a tungsten-containing precursor to finish forming the tungsten nucleation layer.

Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.

Abstract: Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an etchant, and, consequently, the amount of etched material is limited by the amount of adsorbed first reactant. By repeating steps (a) and (b), controlled atomic-scale etching of material is achieved. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where removal of one or multiple atomic layers of material is desired.

Abstract: A semiconductor electroplating process deposits copper into the through silicon via hole to completely fill the through silicon via in a substantially void free is disclosed. The through silicon via may be more than about 3 micrometers in diameter and more that about 20 micrometers deep. High copper concentration and low acidity electroplating solution is used for deposition copper into the through silicon vias.

Abstract: Conductive or barrier material is deposited on a semiconductor substrate having recessed features by a method that has at least two operations. The first operation involves depositing a layer of the material on at least a portion of the field regions of the wafer. The second operation involves resputtering at least the layer residing on the field region of the wafer under high pressure. If the pressure is sufficiently high, momentum transfer reflection of the resputtered material will take place, such that at least some of the resputtered material is placed in the recessed features of the wafer. This approach can, among other advantages, offer improved step coverage and better utilization of the material.

Abstract: Methods and apparatus for improving mechanical properties of a dielectric film on a substrate are provided. In some embodiments, the dielectric film is a carbon-doped oxide (CDO). The methods involve the use of modulated ultraviolet radiation to increase the mechanical strength while limiting shrinkage and limiting any increases in the dielectric constant of the film. Methods improve film hardness, modulus and cohesive strength, which provide better integration capability and improved performance in the subsequent device fabrication procedures such as chemical mechanical polishing (CMP) and packaging.

Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.

Abstract: A liquid injection system for a processing chamber includes a liquid injector that receives a liquid from a liquid supply and that selectively pulses the liquid into a conduit. A control module selects a number of pulses and a pulse width of the liquid injector. A gas supply supplies gas into the conduit. A sensor senses at least one of a first temperature and a first pressure in the conduit and that generates at least one of a first temperature signal and a first pressure signal, respectively. The control module confirms that the selected number of pulses occur based on the at least one of the first temperature signal and the first pressure signal.

Abstract: Functionalized nanoparticles are deposited on metal lines inlaid in dielectric to form a metal cap layer that reduces electromigration in the metal line. The functionalized nanoparticles are deposited onto activated metal surfaces, then sintered and annealed to remove the functional agents leaving behind a continuous capping layer. The resulting cap layer is about 1 to 10 nm thick with 30-100% atomic of the nanoparticle material. Various semiconductor processing tools may be adapted for this deposition process without adding footprint in the semiconductor fabrication plant.

Abstract: Provided are apparatuses and methods disclosed for wafer processing. Specific embodiments include dual wafer handling systems that transfer wafers from storage cassettes to processing modules and back and aspects thereof. Stacked independent loadlocks that allow venting and pumping operations to work in parallel and may be optimized for particle reduction are provided. Also provided are annular designs for radial top down flow during loadlock vent and pumpdown.

Abstract: This invention provides a high throughput PECVD process for depositing TEOS films in a multi-station sequential deposition chamber. The methods significantly reduce the number of particles in the TEOS films, thereby eliminating or minimizing small bin defects. The methods of the invention involve dedicating a first station for temperature soak while flowing purge gas. Stopping the flow of reactant gas and flowing the purge gas for station 1 eliminates TEOS condensation on a cold wafer surface and significantly reduces the number of defects in the film, particularly for short temperature soaks.

Abstract: The present invention provides methods of repairing damage to low-k dielectric film that is incurred by commonly used processes in IC fabrication. The methods may be integrated into an IC fabrication process flow at various stages. According to various embodiments, the methods of involve performing an IC fabrication process on a wafer on which a low-k film is deposited, and subsequently treating the film with a silylating agent to repair the damage done to the film during the process. Damage repair may be performed after one or more of the damaging process steps.

Abstract: Apparatuses and methods for cooling and transferring wafers from low pressure environment to high pressure environment are provided. An apparatus may include a cooling pedestal and a set of supports for holding the wafer above the cooling pedestal. The average gap between the wafer and the cooling pedestal may be no greater than about 0.010 inches. Venting gases may be used to increase the pressure inside the apparatus during the transfer. In certain embodiment, venting gases comprise nitrogen.

Abstract: Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.