Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: Stability of an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer is critical for successful integration. UV-resistant diffusion barrier layers are formed by depositing the layer in a hydrogen-starved environment. Diffusion barrier layers can be made more resistant to UV radiation by thermal, plasma, or UV treatment during or after deposition. Lowering the modulus of the diffusion barrier layer can also improve the resistance to UV radiation.

Abstract: Methods, apparatuses, and various apparatus components, such as base plates, lipseals, and contact ring assemblies are provided for reducing contamination of the contact area in the apparatuses. Contamination may happen during removal of semiconductor wafers from apparatuses after the electroplating process. In certain embodiments, a base plate with a hydrophobic coating, such as polyamide-imide (PAI) and sometimes polytetrafluoroethylene (PTFE), are used. Further, contact tips of the contact ring assembly may be positioned further away from the sealing lip of the lipseal. In certain embodiments, a portion of the contact ring assembly and/or the lipseal also include hydrophobic coatings.

Abstract: Provided are magnetically actuated wafer chucks that permit a wafer to be clamped or unclamped at any time during a process and at any rotational speed, as desired. Such wafer chucks may include constraining members that are movable between open and closed positions. In a closed position, a constraining member aligns the wafer after wafer handoff and/or clamps the wafer during rotation to prevent it from flying off the chuck. In an open position, the constraining member moves away from the wafer to allow liquid etchant to flow from the wafer edge without obstruction. The constraining members may be, for example, cams, attached to arms or links of the chuck. The cams or other constraining members move between open and closed positions by self-balancing forces including a first force, such as a spring force, that acts to move a cam in a first direction, and a non-contact actuate-able force, such as a magnetic force, that acts to move the cam in the opposite direction.

Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.

Abstract: Process chamber shields having specially profiled edges exhibit increased lifetime in PVD and CVD deposition chambers. Edge profiling reduces flaking and delamination of materials deposited onto the shields, thereby prolonging shield life, and, consequently, reducing costs associated with deposition. In one embodiment, a shield having an edge portion terminating in a rounded tip, where the tip has high curvature and a small thickness, is provided. In another aspect, a shield having a concave portion connecting with an edge portion, where an upper (inner) surface of the edge portion forms a tangent plane to the upper (inner) concave surface of the concave surface, is provided. In yet another aspect, a shield with a tapered edge portion is provided. Shields, having profiled edges in accordance with these aspects and in accordance with combinations of these aspects, can better support deposited films, particularly films containing compressively stressed materials, such as metal nitrides.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: Methods of processing partially manufactured semiconductor substrates with one or more through silicon vias to partially remove a tungsten layer formed on the field region during filling the through silicon vias are provided. In certain embodiments, the methods produce substrates with reduced bowing than the bowing present after through silicon vias filling. Substrates with reduced bowing are easier to handle and may expedite subsequent processes.

Abstract: A semiconductive counter electrode covers a highly electronically conductive electric current buss. The semiconductive counter electrode is impervious to ion flow. A substrate holder is operable to hold a substrate and to form a thin fluid gap between the semiconductive counter electrode and a substrate surface. A thin liquid electrolyte layer is located in the thin fluid gap. A power supply connected to the electric current buss and a peripheral edge of a conductive substrate surface is able to generate a potential difference between the electric current buss and the semiconductive counter electrode, on one side of the electrolyte layer, and the substrate on the other side. The semiconductive counter electrode provides a substantial resistance in the various current flow paths between the electric current buss and the semiconductive counter electrode, on one side, and the conductive substrate surface, on the other, thereby enhancing control of current distribution.

Abstract: The present invention relates to curing of semiconductor wafers. More particularly, the invention relates to cure chambers containing multiple cure stations, each featuring one or more UV light sources. The wafers are cured by sequential exposure to the light sources in each station. In some embodiments, the wafers remain stationary with respect to the light source during exposure. In other embodiments, there is relative movement between the light source and the wafer during exposure. The invention also provides chambers that may be used to independently modulate the cross-linking, density and increase in stress of a cured material by providing independent control of the wafer temperature and UV intensity.

Abstract: A temperature controlled showerhead for chemical vapor deposition (CVD) chambers enhances heat dissipation to enable accurate temperature control with an electric heater. Heat dissipates by conduction through a showerhead stem and fluid passageway and radiation from a back plate. A temperature control system includes one or more temperature controlled showerheads in a CVD chamber with fluid passageways serially connected to a heat exchanger.

Abstract: In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps without damaging underlying features and little or no incidence of voids or weak spots is provided. A protective layer is deposited to protect underlying features in regions of the substrate having lower feature density so that unwanted material may be removed from regions of the substrate having higher feature density. This protective layer may deposits thicker on a low density feature than on a high density feature and may be deposited using a PECVD process or low sputter/deposition ratio HDP CVD process. This protective layer may also be a metallic oxide layer that is resistant to fluorine etching, such as zirconium oxide (ZrO2) or aluminum oxide (Al2O3).

Abstract: In a copper electroplating apparatus having separate anolyte and catholyte portions, the concentration of anolyte components (e.g., acid or copper salt) is controlled by providing a diluent to the recirculating anolyte. The dosing of the diluent can be controlled by the user and can follow a pre-determined schedule. For example, the schedule may specify the diluent dosing parameters, so as to prevent precipitation of copper salt in the anolyte. Thus, precipitation-induced anode passivation can be minimized.

Abstract: Chemical-mechanical polishing or planarization (CMP) is enhanced with multi-zone slurry delivery. A polishing pad is provided that contacts with the work piece, and a multi-zone platen is displaced proximate to the polishing pad to facilitate slurry delivery. The platen includes multiple fluid distribution layers that each include a fluid-distributing channel extending from a fluid source to a distribution point on layer. The distribution points on each of the fluid distribution layers correspond to different locations on the polishing surface to thereby create multiple fluid-delivery zones on the pad.

Abstract: A method of cleaning a low dielectric constant film in a lithographic process includes providing a dielectric film having thereover a resist composition, the dielectric film having a dielectric constant no greater than about 4.0, and stripping the resist composition to leave a substantially silicon-containing ash residue on the dielectric film. The method then includes contacting the ash residue with plasma comprising an ionized, essentially pure noble gas such as helium to remove the resist residue without substantially affecting the underlying dielectric film.

Abstract: Top-down methods of increasing reflectivity of tungsten films to form films having high reflectivity, low resistivity and low roughness are provided. The methods involve bulk deposition of tungsten followed by a removing a top portion of the deposited tungsten. In particular embodiments, removing a top portion of the deposited tungsten involve exposing it to a fluorine-containing plasma. The methods produce low resistivity tungsten bulk layers having lower roughness and higher reflectivity. The smooth and highly reflective tungsten layers are easier to photopattern than conventional low resistivity tungsten films. Applications include forming tungsten bit lines.

Abstract: Provided are methods of stabilizing an underlying dielectric diffusion barrier during deposition and ultraviolet (UV) processing of an overlying dielectric layer. Methods include modulating the optical properties reduces the effects of UV radiation on the dielectric diffusion barrier layer. The dielectric diffusion barrier can be made to absorb less UV radiation. A dielectric layer with UV absorbing properties may also be added on top of the diffusion barrier layer so less UV is transmitted. Both methods result in reduced interaction between UV radiation and the dielectric diffusion barrier.

Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.

Abstract: Fault detection apparatuses and methods for detecting a processing or hardware performance fault of a semiconductor production tool have been provided. In an exemplary embodiment, a method for detecting a fault of a semiconductor production tool includes sensing a signal associated with a test component of the production tool during operation of the production tool and converting the signal to an electronic test signal. A prerecorded signature signal corresponding to the test component is provided and the test signal and the prerecorded signature signal are compared.

Abstract: Methods of filling high aspect ratio features provided on partially manufactured semiconductor substrates with tungsten-containing materials are provided. In certain embodiments, the methods include partial filling a high aspect ratio feature with a layer of tungsten-containing materials and selective removal of the partially filled materials from the feature cavity. Substrates processed using these methods have improved step coverage of the tungsten-containing materials filled into the high aspect ratio features and reduced seam sizes.