Abstract: A robot for use in vacuum chambers is disclosed. The robot may be mounted within an oblong transfer chamber and may be translated within the transfer chamber by an umbilical arm operating in conjunction with a linear motion guide and carriage. Motors or drive systems for the robot may be housed in atmospheric conditions, and the transfer chamber may be kept at a vacuum. The robot may include one or more arms configured for wafer handling. The robot may include one or more motors or drive systems and a multi-axial seal to realize independent extension/retraction of each arm and overall simultaneous rotation of the arm assembly.

Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

Abstract: Provided are plasma enhanced chemical vapor deposition methods of depositing smooth and conformal ashable hard mask films on substrates containing raised or recessed features. The methods involve using precursors having relatively high C:H ratios, such as acetylene (C:H ratio of 1), and plasmas having low ion energies and fluxes. According to various embodiments, the methods involve depositing smooth ashable hard mask films using high frequency radio frequency-generated plasmas with no low frequency component and/or relatively high pressures. Also provided are methods of depositing ashable hard mask films having good selectivity and improved side wall coverage and roughness. The methods involve depositing a first ashable hard mask film on a substrate having a feature using a process optimized for selectivity and/or optical properties and then depositing a smoothing layer on the first ashable hard mask film using an HF-only process.

Abstract: Provided are methods and systems for providing silicon carbide class of films. The composition of the silicon carbide film can be controlled by the choice of the combination of precursors and the ratio of flow rates between the precursors. The silicon carbide films can be deposited on a substrate by flowing two different organo-silicon precursors to mix together in a reaction chamber. The organo-silicon precursors react with one or more radicals in a substantially low energy state to form the silicon carbide film. The one or more radicals can be formed in a remote plasma source.

Abstract: Provided are methods of void-free tungsten fill of high aspect ratio features. According to various embodiments, the methods involve a reduced temperature chemical vapor deposition (CVD) process to fill the features with tungsten. In certain embodiments, the process temperature is maintained at less than about 350° C. during the chemical vapor deposition to fill the feature. The reduced-temperature CVD tungsten fill provides improved tungsten fill in high aspect ratio features, provides improved barriers to fluorine migration into underlying layers, while achieving similar thin film resistivity as standard CVD fill. Also provided are methods of depositing thin tungsten films having low-resistivity. According to various embodiments, the methods involve performing a reduced temperature low resistivity treatment on a deposited nucleation layer prior to depositing a tungsten bulk layer and/or depositing a bulk layer via a reduced temperature CVD process followed by a high temperature CVD process.

Abstract: Disclosed herein are lipseal assemblies for use in electroplating clamshells which may include an elastomeric lipseal for excluding plating solution from a peripheral region of a semiconductor substrate and one or more electrical contact elements. The contact elements may be structurally integrated with the elastomeric lipseal. The lipseal assemblies may include one or more flexible contact elements at least a portion of which may be conformally positioned on an upper surface of the elastomeric lipseal, and may be configured to flex and form a conformal contact surface that interfaces with the substrate. Some elastomeric lipseals disclosed herein may support, align, and seal a substrate in a clamshell, and may include a flexible elastomeric upper portion located above a flexible elastomeric support edge, the upper portion having a top surface and an inner side surface, the later configured to move inward and align the substrate upon compression of the top surface.

Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.

Abstract: Disclosed herein are cleaning discs for cleaning one or more elements of a semiconductor processing apparatus. In some embodiments, the disc may have a substantially circular upper surface, a substantially circular lower surface, a substantially circular edge joining the upper and lower surfaces, and a plurality of pores opening at the edge and having an interior extending into the interior of the disc. In some embodiments, the pores are dimensioned such that a cleaning agent may be retained in the interior of the pores by an adhesive force between the cleaning agent and the interior surface of the pores. Also disclosed herein are cleaning methods involving loading a cleaning agent into a plurality of pores of a cleaning disc, positioning the cleaning disc within a semiconductor processing apparatus, and releasing cleaning agent from the plurality of pores such that elements of the apparatus are contacted by the released cleaning agent.

Abstract: Systems, system components, and methods for plasma stripping are provided. In an embodiment, a gas flow distribution receptacle may have a rounded section that includes an inner surface defining a reception cavity, an outer surface forming an enclosed end, and a centerpoint on the outer surface having a longitudinal axis extending therethrough and through the reception cavity. First and second rings of openings provide flow communication with the plasma chamber. The second ring of openings are disposed between the first ring and the centerpoint, and each opening of the second ring of openings extends between the inner and outer surfaces at a second angle relative to the longitudinal axis that is less than the first angle and has a diameter that is substantially identical to a diameter of an adjacent opening and smaller than the diameters of an opening of the first ring of openings.

Abstract: Methods of processing a substrate include supplying process gas to a processing chamber including the substrate. Plasma is created in the processing chamber. After performing a first substrate processing step, the plasma is maintained in the processing chamber and at least one operating parameter is adjusted. The operating parameters may include RF bias to a pedestal, a plasma voltage bias, a gas admixture, a gas flow, a gas pressure, an etch to deposition (E/D) ratio and/or combinations thereof. One or more additional substrate processing steps are performed without an interruption in the plasma between the first substrate processing step and the one or more additional substrate processing steps.

Abstract: A substrate processing system includes one or more processing chambers defining N reaction volumes. N-1 first valves are arranged between the N reaction volumes. A controller communicates with the N-1 first valves and is configured to pressurize a first one of the N reaction volumes with precursor gas to a first target pressure, wait a first predetermined soak period, evacuate a second one of the N reaction volumes to a second target pressure that is lower than the first target pressure, and open one of the N-1 first valves between the first one of the N reaction volumes and a second one of the N reaction volumes.

Abstract: The methods and apparatus disclosed herein concern a process that may be referred to as a “soft anneal.” A soft anneal provides various benefits. Fundamentally, it reduces the internal stress in one or more silicon layers of a work piece. Typically, though not necessarily, the internal stress is a compressive stress. A particularly beneficial application of a soft anneal is in reduction of internal stress in a stack containing two or more layers of silicon. Often, the internal stress of a layer or group of layers in a stack is manifest as wafer bow. The soft anneal process can be used to reduce compressive bow in stacks containing silicon. The soft anneal process may be performed without causing the silicon in the stack to become activated.

Abstract: An apparatus for conditioning deionized water and delivering it to a semiconductor wafer in a post electrofill module includes a degassing station configured to remove dissolved gas from the deionized water flow, a heating station configured to heat the deionized water flow, and a nozzle configured to deliver the deionized water flow to the wafer. The heating and degassing are performed before the delivery of the deionized water flow to the wafer. In some implementations the degassing station includes a contact degasser or an inert gas bubbler, and the heating station is configured to heating the deionized water flow to a temperature of between about 35-40° C. In some embodiments the deionized water flow is passed through the degassing station before being passed through the heating station.

Abstract: An electrolyte, and particularly anolyte, may be circulated via an open loop having a pressure regulator, so that the pressure in the plating chamber is maintained at a constant (or substantially constant) value with respect to atmospheric pressure. In these embodiments, a pressure regulator is in fluid communication with the anode chamber.

Abstract: Apparatuses and techniques for providing for variable radial flow conductance within a semiconductor processing showerhead are provided. In some cases, the radial flow conductance may be varied dynamically during use. In some cases, the radial flow conductance may be fixed but may vary as a function of radial distance from the showerhead centerline. Both single plenum and dual plenum showerheads are discussed.

Abstract: A layer of diffusion barrier or seed material is deposited on a semiconductor substrate having a recessed feature. The method may include a series of new deposition cycles, for example, a first net deposition cycle and a second net deposition cycle. The first net deposition cycle includes depositing a first deposited amount of the diffusion barrier or seed material and etching a first etched amount of the diffusion barrier or seed material. The second net deposition cycle including depositing a second deposited amount of the diffusion barrier or seed material and etching a second etched amount of the diffusion barrier or seed material. At least one of the process parameters of the first cycle differs from that of the second allows providing a graded deposition effects to reduce a risk of damaging any under layers and dielectric. A deposited layer of diffusion barrier or seed material is generally more conformal.

Abstract: Smooth silicon films having low compressive stress and smooth tensile silicon films are deposited by plasma enhanced chemical vapor deposition (PECVD) using a process gas comprising a silicon-containing precursor (e.g., silane), argon, and a second gas, such as helium, hydrogen, or a combination of helium and hydrogen. Doped smooth silicon films and smooth silicon germanium films can be obtained by adding a source of dopant or a germanium-containing precursor to the process gas. In some embodiments dual frequency plasma comprising high frequency (HF) and low frequency (LF) components is used during deposition, resulting in improved film roughness. The films are characterized by roughness (Ra) of less than about 7 ?, such as less than about 5 ? as measured by atomic force microscopy (AFM), and a compressive stress of less than about 500 MPa in absolute value. In some embodiments smooth tensile silicon films are obtained.

Abstract: An electroplating apparatus for filling recessed features on a semiconductor substrate includes an electrolyte concentrator configured for concentrating an electrolyte having Cu2+ ions to form a concentrated electrolyte solution that would have been supersaturated at 20° C. The electrolyte is maintained at a temperature that is higher than 20° C., such as at least at about 40° C. The apparatus further includes a concentrated electrolyte reservoir and a plating cell, where the plating cell is configured for electroplating with concentrated electrolyte at a temperature of at least about 40° C. Electroplating with electrolytes having Cu2+ concentration of at least about 60 g/L at temperatures of at least about 40° C. results in very fast copper deposition rates, and is particularly well-suited for filling large, high aspect ratio features, such as through-silicon vias.

Abstract: A plasma ignition system includes a first voltage supply that selectively supplies a plasma ignition voltage and a plasma maintenance voltage across an adapter ring and a cathode target of a physical vapor deposition (PVD) system. A second voltage supply selectively supplies a second voltage across the adapter ring and an anode ring of the PVD system. A plasma ignition control module ignites plasma using the plasma ignition voltage and the auxiliary plasma ignition voltage and, after the plasma ignites, supplies the plasma maintenance voltage and ceases supplying the plasma ignition voltage and the auxiliary plasma ignition voltage.

Abstract: The present invention pertains to methods for forming a metal diffusion barrier on an integrated circuit wherein the formation includes at least two operations. The first operation deposits barrier material via PVD or CVD to provide some minimal coverage. The second operation deposits an additional barrier material and simultaneously etches a portion of the barrier material deposited in the first operation. The result of the operations is a metal diffusion barrier formed in part by net etching in certain areas, in particular the bottom of vias, and a net deposition in other areas, in particular the side walls of vias. Controlled etching is used to selectively remove barrier material from the bottom of vias, either completely or partially, thus reducing the resistance of subsequently formed metal interconnects.