Patents Assigned to Numerical Technology, Inc.
  • Patent number: 6928635
    Abstract: One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.
    Type: Grant
    Filed: September 25, 2002
    Date of Patent: August 9, 2005
    Assignee: Numerical Technologies, Inc.
    Inventors: Dipankar Pramanik, Michael Sanie
  • Publication number: 20050130047
    Abstract: When substantially all features in a layout for a layer of material in an integrated circuit (IC) are defined using a phase shifting mask, the related complementary mask that is normally used to define the remaining features and edges can be improved if intensities in an aerial image from openings on the complementary mask that are below threshold are increased to ensure that each opening meets or exceeds threshold. Such increase of intensities improves effectiveness of critical openings that are otherwise too small to print. Absent intensity increase, such openings could limit the application of optical lithography using phase shifting masks to ever shrinking technologies. The intensities are increased in some embodiments by enlarging some openings in the complementary mask in directions not constrained by features to be formed in an integrated circuit (by use of the phase shifting mask).
    Type: Application
    Filed: December 11, 2003
    Publication date: June 16, 2005
    Applicant: Numerical Technologies, Inc. a wholly owned subsidiary of Synopsys, Inc.
    Inventor: Armen Kroyan
  • Patent number: 6901575
    Abstract: A method of assigning phases to shifters on a layout is provided. The method includes creating a link between any two shifters within a predetermined distance from each other. In one embodiment, the predetermined distance is larger than a minimum feature size on the layout, and smaller than a combined minimum pitch and regulator width. A weight can be assigned to each created link. Phases can be assigned to the shifters, wherein if a phase-shift conflict exists on the layout, then one or more links can be broken based on their weight.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: May 31, 2005
    Assignee: Numerical Technologies, Inc.
    Inventors: Shao-Po Wu, Seonghun Cho, Yao-Ting Wang
  • Patent number: 6870951
    Abstract: One embodiment of the invention provides a system that facilitates auto-alignment of images for defect inspection and defect analysis. The system operates by first receiving a reference image and a test image. Next, the system creates a horizontal cut line across the reference image and chooses a vertical feature on the reference image with a specified width along the horizontal cut line. The system also creates a vertical cut line across the reference image and chooses a horizontal feature on the reference image with the specified width along the vertical cut line. Finally, the system locates the vertical feature and the horizontal feature on the test image so that the reference image and the test image can be aligned to perform defect inspection and defect analysis.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: March 22, 2005
    Assignee: Numerical Technologies, Inc.
    Inventor: Lynn Cai
  • Publication number: 20050060682
    Abstract: A method of assigning phases to shifters on a layout is provided. The method includes creating a link between any two shifters within a predetermined distance from each other. In one embodiment, the predetermined distance is larger than a minimum feature size on the layout, and smaller than a combined minimum pitch and regulator width. A weight can be assigned to each created link. Phases can be assigned to the shifters, wherein if a phase-shift conflict exists on the layout, then one or more links can be broken based on their weight.
    Type: Application
    Filed: November 3, 2004
    Publication date: March 17, 2005
    Applicant: Numerical Technologies, Inc.
    Inventors: Shao-Po Wu, Seonghun Cho, Yao-Ting Wang
  • Publication number: 20050031971
    Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.
    Type: Application
    Filed: September 10, 2004
    Publication date: February 10, 2005
    Applicant: Numerical Technologies, Inc.
    Inventors: Michel Cote, Christophe Pierrat
  • Publication number: 20050031972
    Abstract: A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.
    Type: Application
    Filed: September 10, 2004
    Publication date: February 10, 2005
    Applicant: Numerical Technologies, Inc.
    Inventors: Michel Cote, Christophe Pierrat
  • Patent number: 6852471
    Abstract: Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0<r<4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.
    Type: Grant
    Filed: October 5, 2001
    Date of Patent: February 8, 2005
    Assignee: Numerical Technologies, Inc.
    Inventors: Christophe Pierrat, Michel Luc Côté
  • Patent number: 6846596
    Abstract: A method and system produce alternating phase shift masks using multiple phase shift mask resolution levels for multiple feature classes. In one method, a pattern for a photolithographic mask that defines a layer is processed, The pattern defines features in multiple feature classes in the layer. For various feature resolution levels, layout dimensions for phase shift windows pairs are defined. The phase shift windows pairs are laid out with the layout dimensions. Phase shift values are assigned to the phase shift windows.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: January 25, 2005
    Assignee: Numerical Technologies, Inc.
    Inventor: Shao-Po Wu
  • Patent number: 6830854
    Abstract: An accurate, cost-effective system and method for correcting 3D effects on an alternating phase-shifting mask (PSM) is provided. To facilitate this correction, a library can be built to include a first group of 180 degree phase-shifting regions, wherein these regions have a common first size. Based on this first size, 3D simulation is performed. A transmission and a phase are altered in a 2D simulation based on this first size until a shape dependent transmission and a shape dependent phase allow the 2D simulation to substantially match the 3D simulation. Finally, a modified first size is chosen using the shape dependent transmission and the shape dependent phase such that a 2D simulation based on the modified first size substantially matches the 3D simulation based on the first size. The library associates the first size with the modified first size, the shape dependent transmission, and the shape dependent phase.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: December 14, 2004
    Assignee: Numerical Technologies, Inc.
    Inventors: Yong Liu, Hua-Yu Liu
  • Publication number: 20040243320
    Abstract: A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask.
    Type: Application
    Filed: June 28, 2004
    Publication date: December 2, 2004
    Applicant: NUMERICAL TECHNOLOGIES, INC.
    Inventors: Fang-Cheng Chang, Yao-Ting Wang, Yagyensh C. Pati, Linard N. Karklin
  • Patent number: 6823503
    Abstract: One embodiment of the invention provides a system that creates a phase-shifting mask for a photolithographic process used in fabricating an integrated circuit. The system starts by receiving a layout for the integrated circuit. The system then associates nodes with features in the layout, and generates arcs between the nodes. Next, the system generates a coloring for the nodes using two colors. The system then generates phase shifters for the phase-shifting mask and assigns different phases to the phase shifters based upon the coloring of the nodes.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: November 23, 2004
    Assignee: Numerical Technologies, Inc.
    Inventor: Kevin A. Beaudette
  • Patent number: 6818385
    Abstract: A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: November 16, 2004
    Assignee: Numerical Technologies, Inc.
    Inventors: Yao-Ting Wang, Yagyensh C. Pati
  • Publication number: 20040218831
    Abstract: Resolution enhancement techniques (RETs) aid in accurately transferring features on a layout to a wafer. Unfortunately, RETs may work well at one pitch but not another pitch. If image quality falls below an acceptable threshold at a certain pitch, then such a pitch is called a forbidden pitch. A cell library cell that can automatically avoid forbidden pitches is provided. In this method, evaluation points on edges of a feature in a cell can be analyzed based on a RET and a lithography model. Using this analysis, any forbidden pitch for the feature can be identified. Additionally, any forbidden pitch can be changed to an acceptable pitch, i.e. a pitch resulting in an acceptable image quality. The forbidden pitch information and the associated acceptable pitch information for the feature can be stored in a database to facilitate analyzing other features/cells.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 4, 2004
    Applicant: Numerical Technologies, Inc.
    Inventor: Hua-Yu Liu
  • Publication number: 20040221255
    Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge.
    Type: Application
    Filed: May 26, 2004
    Publication date: November 4, 2004
    Applicant: Numerical Technologies, Inc.
    Inventors: Christophe Pierrat, Youping Zhang
  • Patent number: 6813759
    Abstract: One embodiment of the invention provides a system that facilitates optical proximity correction for alternating aperture phase shifting designs. During operation, the system receives a layout, which includes a complementary mask and a phase shifting mask. A subset of trim features on the complementary mask that are designed to protect the dark areas left unexposed by the phase shifting mask are adjusted first using a rules-based optical proximity correction process. This is then supplemented by a model-based correction to the phase shifters, Additionally, the portions of the trim that are co-extensive with the original layout can be corrected, e.g. at the time of the correction of the complementary mask using either rule or model based corrections.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: November 2, 2004
    Assignee: Numerical Technologies, Inc.
    Inventors: Hua-yu Liu, Weinong Lai, Xiaoyang Li
  • Patent number: 6811935
    Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. In one approach, phase shift regions are laid out so that they extend around corners in a feature, and in one or more identified corners having greater process latitude, the phase shift regions are divided and assigned opposite phases in the corner.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: November 2, 2004
    Assignee: Numerical Technologies, Inc.
    Inventor: Christophe Pierrat
  • Patent number: 6808850
    Abstract: One embodiment of the invention provides a system that performs optical proximity correction (OPC) on selected segments on a trim mask used in fabricating an integrated circuit. Upon receiving the trim mask, the system identifies selected segments on the trim mask that do not abut any feature to be printed on the integrated circuit. Next, the system performs a number of OPC operations. The system performs a first OPC operation on the selected segments to correct the selected segments. The system also performs a second OPC operation to correct segments on the trim mask that do abut features to be printed on the integrated circuit. The system additionally performs a third OPC operation on an associated phase shifting mask to correct segments that abut features to be printed on the integrated circuit. (Note that the first, second and third OPC operations can be performed separately or at the same time.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: October 26, 2004
    Assignee: Numerical Technologies, Inc.
    Inventor: Christophe Pierrat
  • Publication number: 20040209193
    Abstract: Mask and integrated circuit fabrication approaches are described to facilitate use of so called “full phase” masks. This facilitates use of masks where substantially all of a layout is defined using phase shifting. More specifically, exposure settings including relative dosing between the phase shift mask and the trim masks are described. Additionally, single reticle approaches for accommodating both masks are considered. In one embodiment, the phase shifting mask and the trim mask are exposed using the same exposure conditions, except for relative dosing. In another embodiment, the relative dosing between the phase and trim patterns is 1.0:r, 2.0<r<4.0. These approaches facilitate better exposure profiles for the resulting ICs and can thus improve chip yield and increase throughput by reducing the need to alter settings and/or switch reticles between exposures.
    Type: Application
    Filed: May 7, 2004
    Publication date: October 21, 2004
    Applicant: Numerical Technologies, Inc.
    Inventors: Christophe Pierrat, Michel Luc Cote
  • Publication number: 20040209176
    Abstract: Shifters on a phase shifting mask (PSM) can be intelligently assigned their corresponding phase. Specifically, the phase of a shifter can be assigned based on simulating the contrast provided by each phase for that shifter. The higher the contrast, the better the lithographic performance of the shifter. Therefore, the phase providing the higher contrast can be selected for that shifter. To facilitate this phase assignment, a pre-shifter can be placed relative to a feature on the layout. The pre-shifter can then be divided into a plurality of shifter tiles for contrast analysis. Model-based data conversion allows for a comprehensive solution including both phase assignment as well as optical proximity correction.
    Type: Application
    Filed: May 12, 2004
    Publication date: October 21, 2004
    Applicant: Numerical Technologies, Inc.
    Inventor: Christophe Pierrat