Abstract: Shifters on a phase shifting mask (PSM) can be intelligently assigned their corresponding phase. Specifically, the phase of a shifter can be assigned based on simulating the contrast provided by each phase for that shifter. The higher the contrast, the better the lithographic performance of the shifter. Therefore, the phase providing the higher contrast can be selected for that shifter. To facilitate this phase assignment, a pre-shifter can be placed relative to a feature on the layout. The pre-shifter can then be divided into a plurality of shifter tiles for contrast analysis. Model-based data conversion allows for a comprehensive solution including both phase assignment as well as optical proximity correction.

Abstract: A method of optimizing a wafer fabrication process for a given mask is provided. The method includes capturing an image of a mask and simulating a wafer image of the mask. A mask map of information can then be generated based on the simulated wafer image. The resulting mask map can be provided to any downstream wafer fabrication process when such process involves the mask. One or more one input parameters to the downstream wafer fabrication process can be changed based on the mask map, thereby optimizing the process for the given mask.

Abstract: A structure and method are provided for correcting the optical proximity effects on a tri-tone attenuated phase-shifting mask. An attenuated rim, formed by an opaque region and an attenuated phase-shifting region, can be kept at a predetermined width across the mask or for certain types of structures. Typically, the attenuated rim is made as large as possible to maximize the effect of the attenuated phase-shifting region while still preventing the printing of larger portions of the attenuated phase-shifting region during the development process.

Abstract: One embodiment of the invention provides a system that uses pupil filtering to mitigate optical proximity effects that arise during an optical lithography process for manufacturing an integrated circuit. During operation, the system applies a photoresist layer to a wafer and then exposes the photoresist layer through a mask. During this exposure process, the system performs pupil filtering, wherein the pupil filtering corrects for optical proximity effects caused by an optical system used to expose the photoresist layer.

Abstract: A method and system produce alternating phase shift masks using multiple phase shift mask resolution levels for multiple feature classes.

Abstract: A method of modeling an edge profile for a layer of material is provided. The layer of material can include a resist and/or an etch. In this method, multiple models can be generated, wherein at least two models correspond to different elevations on the wafer. Each model includes an optical model, which has been calibrated using test measurements at the respective elevations. In this manner, an accurate edge profile can be quickly created using the multiple models. Based on the edge profile, layout, mask, and/or process conditions can be modified to improve wafer printing.

Abstract: A conductive blank enables election beam (e-beam) patterning rather than optical patterning for the phase level etch of a phase-shifting mask (PSM) photomask. The conductive blank includes a conductive layer between a chrome (pattern) layer and a quartz substrate. The chrome layer is patterned with in-phase and phased features, and then is recoated with a resist layer. An e-beam exposure tool exposes the resist layer over the phased features. The still intact conductive layer under the chrome layer dissipates any charge buildup in the resist layer during this process. A phase level etch then etches through the conductive layer and creates a pocket in the quartz. A subsequent isotropic etch through both the in-phase and phased features removes the conductive layer at the in-phase features and improves exposure radiation transmission intensity. Alternatively, a visually transparent conductive layer can be used, eliminating the need to etch through the in-phase features.

Abstract: By using a test pattern that has been corrected according to an optical model to prepare test wafers, better data can be obtained for calibrating the optical model. As a result: fewer measurements need to be taken from the wafer to calibrate the model and the measurements that are taken are more valuable because they better assist in calibrating the model. Embodiments of the invention include data comprising the corrected test pattern, masks including the corrected test pattern, and methods and apparatuses for using the modified test pattern. Additionally, by taking more measurements closer to the target dimensions, more information is available for performing optical proximity correction of layouts. Another benefit includes increased ease of model accuracy determinations.

Abstract: One embodiment of the invention provides a system that facilitates exposing a wafer through at least two masks during an integrated circuit manufacturing process. The system includes a radiation source and two or more illuminators. Each of these illuminators receives radiation from the radiation source, and uses the radiation to illuminate a reticle holder. The radiation that passes through each reticle holder is then combined in an optical combiner, before passing through an imaging optics, which projects the combined radiation onto a semiconductor wafer.

Abstract: A critical dimension, or width, of a feature, or a semiconductor device, can be measured to provide direct and meaningful information regarding the impact of line end shortening, or length, on the function of the device. Specifically, a location on the feature where the width will have an impact on device performance can be selected. Using a simulation, the width at that location can be computed. Given the difficulties of direct measurement of line end shortening and the relationship between the width measurement and the impact on device performance, better layout checking is facilitated than by standard measurements of line end shortening.

Abstract: One embodiment of the invention provides a system that simulates effects of a manufacturing process on an integrated circuit to enhance process latitude and/or reduce layout size. During operation, the system receives a representation of a target layout for the integrated circuit, wherein the representation defines a plurality of shapes that comprise the target layout. Next, the system simulates effects of the manufacturing process on the target layout to produce a simulated printed image for the target layout. The system then identifies problem areas in the specification that no not meet a specification. Next, the system moves corresponding shapes in the target layout to produce a new target layout for the integrated circuit, so that a simulated printed image of the new target layout meets the specification.

Abstract: An automated phase assignment method is described that allows multiple rules for defining phase shifters to be used within a single cell. The rules for defining phase shifters can be sequenced. Then for a cell, the rules can be recursively applied. At each stage if the number of phase conflicts is below a threshold, then portions of the cell having conflicts are masked and processed using the next less aggressive rule set. This in turn leads to phase shifting masks with greater variation in phase shifter shapes and sizes. When the mask is used to fabricate integrated circuits (ICs), the resulting IC may have a greater number of small transistors and other features than a mask defined using only a single rule set per cell. Additional benefits can include better process latitude during IC fabrication and improved yield.

Abstract: One embodiment of the invention provides a system for speeding up processing of a layout of an integrated circuit that has been divided into cells. The system operates by determining if a target cell in the layout is identical to a preceding cell for which there exists a previously calculated solution by comparing an identifier created from the target cell with an identifier created from the preceding cell. If the target cell is identical to a preceding cell, the system uses the previously calculated solution as a solution for the target cell. Otherwise, if the target cell is not identical to the preceding cell, the system processes the target cell to produce the solution for the target cell. Note that this approach can also be used for a number of different processes, such as distributed fracturing or optical proximity correction.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Abstract: One embodiment of the invention provides a system for speeding up an iterative process that simulates and, if necessary, corrects a layout of a target cell within an integrated circuit so that a simulated layout of the target cell matches a desired layout for the target cell. The system operates by determining if the target cell is similar to a preceding cell for which there exists a previously calculated solution. If so, the system uses the previously calculated solution as an initial input to the iterative process that produces the solution for the target cell.

Abstract: Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates one or more features logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. The adjustments rearrange features in a unit of the design layout to collect free space around a selected feature associated with the phase-shift conflict. With these techniques, a unit needing more space for additional shifters can obtain the needed space during the physical design process making the adjustment. The needed space so obtained allows the fabrication design process to avoid or resolve phase conflicts while forming a fabrication layout, such as a mask, for substantiating the design layout in a printed features layer, such as in an actual integrated circuit.

Abstract: A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.

Abstract: To print sub-wavelength features on a wafer, a mask set including a full phase PSM (FPSM) and a corresponding trim mask can be used. Phase assignments on the FPSM can result in some feature definition with the trim mask, particularly in non-critical areas. Unfortunately, this limited feature definition can cause significant critical dimension (CD) variations in these non-critical areas. Undesirable critical dimension (CD) variations can be better controlled, even with substantial mask misalignment, by defining multiple feature edge portions with the trim mask in non-critical areas, such as T-intersections, elbows, and other types of intersecting lines.

Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.

Abstract: Techniques are provided for extending the use of phase shift techniques to implementation of masks used for complex “double-T” layouts in the layers of integrated circuits, beyond selected critical dimension features such as transistor gates to which such structures have been limited in the past. The method includes identifying features, including “double-T” features, for which phase shifting can be applied, automatically mapping the phase shifting regions for implementation of such features, resolving phase conflicts which might occur according to a given design rule, and application of sub-resolution assist features within phase shift regions and optical proximity correction features to phase shift regions. Both opaque field phase shift masks and complementary binary masks defining interconnect structures and other types of structures that are not defined using phase shifting, necessary for completion of the layout of the layer are produced.