Patents Assigned to NUVOTON TECHNOLOGY CORPORATION JAPAN
  • Patent number: 11139848
    Abstract: A communication system including a transmission device and a reception device which wirelessly communicate with each other. The transmission device includes a transmission circuit that performs: cyclical transmission of a wake-up signal including a specific pattern; and transmission of data. The reception device includes: a standby circuit that receives a signal, and outputs a detection signal indicating reception of the wake up signal when detecting that the specific pattern is cyclically included in the signal received; and a reception circuit that receives the data from the transmission device after the detection signal is output from the standby circuit.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 5, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Kenichi Hoshi, Ryoichi Suzuki, Akifumi Nagao, Kentaro Watanabe
  • Patent number: 11115611
    Abstract: A solid-state imaging device includes a first converter which converts an analog signal representing a pixel value to an upper bit of a digital signal, and a second converter which converts the analog signal to a lower bit of the digital signal. The second converter includes a first latch circuit which latches, as phase information, a plurality of clock signals having different phases upon conversion to the upper bit in the first converter, a conversion circuit which generates the lower bit of the digital signal by converting the phase information to a binary value, and an adder, and a second latch circuit which latches an addition result of the adder. The adder adds the binary value converted by the conversion circuit and a value latched by the second latch circuit.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: September 7, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Yosuke Higashi, Norihiko Sumitani
  • Patent number: 11115009
    Abstract: A semiconductor integrated circuit includes a first flip-flop that includes a first slave latch, a second flip-flop that includes a second slave latch, and a clock generation circuit that provides a common clock signal to the first flip-flop and the second flip-flop. The first slave latch includes a first inverter, a first feedback inverter that receives an output signal from the first inverter, and a first switch that is connected between an input terminal of the first inverter and an output terminal of the first feedback inverter. The first flip-flop outputs an output signal from the output terminal of the first feedback inverter.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: September 7, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventor: Kazuyuki Nakanishi
  • Patent number: 11107915
    Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: August 31, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Chie Fujioka, Hiroshi Yoshida, Yoshihiro Matsushima, Hideki Mizuhara, Masao Hamasaki, Mitsuaki Sakamoto
  • Patent number: 11089270
    Abstract: A solid-state imaging device includes pixels arranged in matrix form, each including a photoelectric converter and first transfer electrodes, and control lines connected to mutually-corresponding ones of the first transfer electrodes in pixels arranged in a specific row. The pixels include first pixels that receive visible light and second pixels that receive infrared light. Each of floating diffusion layer-including pixels, which are some of the plurality of pixels, further includes a floating diffusion layer and a readout circuit. Each floating diffusion layer-lacking pixel shares the floating diffusion layer with one of the first pixels arranged in a column direction. At least some of the control lines are further connected to the first transfer electrodes of pixels arranged adjacent in the column direction to respective ones of the pixels arranged in the specific row and that share at least one of the floating diffusion layers.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 10, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Junichi Matsuo, Sei Suzuki
  • Patent number: 11070028
    Abstract: A semiconductor light emitting element includes: a GaN substrate; a first semiconductor layer located above the GaN substrate and including a nitride semiconductor of a first conductivity type; an active layer located above the first semiconductor layer and including a nitride semiconductor including Ga or In; an electron barrier layer located above the active layer and including a nitride semiconductor including Al; and a second semiconductor layer located above the electron barrier layer and including a nitride semiconductor of a second conductivity type. The electron barrier layer includes: a first region having an Al composition ratio changing at a first change rate; and a second region having an Al composition ratio changing at a second change rate larger than the first change rate. In the first second regions, the Al composition ratio monotonically increases at the first change rate in the direction from the active layer toward second semiconductor layer.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 20, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Toru Takayama, Shinji Yoshida, Kunimasa Takahashi
  • Patent number: 11069783
    Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 20, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
  • Patent number: 11056589
    Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: July 6, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
  • Patent number: 11056563
    Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: July 6, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
  • Patent number: 11049856
    Abstract: Provided is a semiconductor device which is a facedown mounting, chip-size-package-type semiconductor device and includes: a transistor element including a first electrode, a second electrode, and a control electrode which controls a conduction state between the first electrode and the second electrode; a plurality of first resistor elements each including a first electrode and a second electrode, the first electrodes of the first resistor elements being electrically connected to the second electrode of the transistor element; one or more external resistance terminals to which the second electrodes of the plurality of first resistor elements are physically connected; a first external terminal electrically connected to the first electrode of the transistor element; and an external control terminal electrically connected to the control electrode.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: June 29, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Kazuma Yoshida, Ryosuke Okawa, Tsubasa Inoue