Abstract: A touch device and an operation method for the touch device are provided. The touch device includes touch keys, controllers, and a processing circuit. The controllers group selected touch keys among the touch keys into at least one touch key group. Each of the at least one touch key group includes at least two selected touch keys. When the selected touch keys of a first touch key group among the at least one touch key group are simultaneously touched, the processing circuit sequentially provides touch driving signals to the first touch key group and receives touch sensing signal groups corresponding to the touch driving signals. When the touch sensing signal groups all indicate that the selected touch keys of the first touch key group are simultaneously touched, the processing circuit determines that the touch on the first touch key group is a valid touch.

Abstract: Semiconductor light-emitting apparatus includes substrate, submount above substrate, and semiconductor laser above submount. Semiconductor laser and submount are bonded to each other with first bonding material. Substrate and submount are bonded to each other with second bonding material. Submount has first region and second region near substrate, first region being a region on which spacer is disposed, and second region being a region without spacer. Submount is bonded to substrate by covering at least a portion of second region with second bonding material.

Abstract: A touch device and an operation method for the touch device are provided. The touch device includes touch keys, controllers, and a processing circuit. The controllers group selected touch keys among the touch keys into at least one touch key group. Each of the at least one touch key group includes at least two selected touch keys. When the selected touch keys of a first touch key group among the at least one touch key group are simultaneously touched, the processing circuit sequentially provides touch driving signals to the first touch key group and receives touch sensing signal groups corresponding to the touch driving signals. When the touch sensing signal groups all indicate that the selected touch keys of the first touch key group are simultaneously touched, the processing circuit determines that the touch on the first touch key group is a valid touch.

Abstract: In a driving circuit, a drain of first NMOS transistor receives current with a positive temperature coefficient provided by current source, and a gate of first NMOS transistor and a gate of second NMOS transistor are electrically connected to the drain of first NMOS transistor. A drain and a source of second NMOS transistor respectively receive an input voltage and generate an output voltage for driving a load. Two ends of resistor are respectively electrically connected to a source of first NMOS transistor and an emitter of PNP bipolar junction transistor. A base of PNP bipolar junction transistor is electrically connected to a source of second NMOS transistor, and a collector of PNP bipolar junction transistor is electrically connected to a low voltage. By selecting the resistance value of the resistor, an overdrive voltage or a turned-on resistance value of second NMOS transistor is independent of a temperature variation.

Abstract: A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.

Abstract: A battery management circuit is a battery management circuit that manages an energy storage device including battery cells and capacitors, and includes: a first switching circuit that connects a first capacitor among the capacitors and a first battery cell among the battery cells in parallel; a second switching circuit that connects the first capacitor and two or more series-connected battery cells other than the first battery cell among the battery cells in parallel; and a control circuit that performs a first control of repeatedly switching between the connection by the first switching circuit and the connection by the second switching circuit.

Abstract: A power supply device is used to provide power to an encryption and decryption device of a security system, including a safety power supply device, which is used to supply the supply voltage according to the system voltage; a regulated voltage source, which is used to provide a regulated voltage; and a voltage selection device, which is electrically connected with the safety power supply device, the stable voltage source and the encryption and decryption device. During the startup period of the security system, or, after the startup period of the security system and the encryption/decryption device performs encryption/decryption, only the supply voltage is selected as the driving voltage of the encryption/decryption device. After the startup period of the security system and the encryption and decryption device does not perform encryption and decryption, the voltage only the regulated voltage is selected as the driving voltage of the encryption and decryption device.

Abstract: A variable resistance nonvolatile storage device includes: a variable resistance element having a state reversibly changeable between a high resistance state and a low resistance state; and a current supply circuit that supplies the variable resistance element with a low-resistance changing current for changing the state from the high resistance state to the low resistance state. The low-resistance changing current has a waveform that includes a first period and a second period along a time axis, the second period being subsequent to the first period. The current supply circuit applies to the variable resistance element: a first current during the first period; and a second current during the second period, the second current being smaller than the first current. The first current is not zero at an end of the first period, and the second current is not zero at a start of the second period.

Abstract: A distance-measuring imaging device includes: a timing controller that outputs one or more timing signals; a light receiver that receives reflected light that is light emitted by a light source and reflected by a subject; a phase adjustment circuit that outputs at least one signal out of a light emission control signal and an exposure control signal, based on the one or more timing signals, the light emission control signal being used for causing the light source to emit light to the subject, the exposure control signal being used for causing the light receiver to start exposure. The phase adjustment circuit includes one or more DLL circuits each of which determines, for at least one of the one or more timing signals, at least one of a phase of a rising edge or a phase of a falling edge of the at least one signal.

Abstract: A semiconductor laser element includes: a first conductivity-type cladding layer; a first guide layer disposed above the first conductivity-type cladding layer; an active layer disposed above the first guide layer; and a second conductivity-type cladding layer disposed above the active layer. A window region is formed in a region of the active layer including part of at least one of the front-side end face or the rear-side end face, the first conductivity-type cladding layer consists of (AlxGa1-x)0.5In0.5P, the first guide layer consists of (AlyGa1-y)0.5In0.5P, and the second conductivity-type cladding layer consists of (AlzGa1-z)0.5In0.5P, where x, y, and z each denote an Al composition ratio, 0<x?y<z?y is satisfied, and D/L>0.03 is satisfied, where L denotes a length of the resonator and D denotes a length of the window region in the first direction.

Abstract: A security system configured for deployment on a chip which is to be protected, the system comprising fault injection detection subsystem/s configured for deployment on the chip, each fault injection detection subsystem having plural sensitivity levels which are selectable in real time and comprising at least one hardware fault injection detector circuit/s, configured for deployment on the chip, and/or, coupled thereto, sensitivity level control logic which may be configured for deployment on the chip and which may be operative, in real time, to transition the fault injection detection subsystem, from its current sensitivity level from among said plural selectable sensitivity levels, to a next sensitivity level from among said plural selectable sensitivity levels, e.g. by generating sensitivity control signals (aka sensitivity level selections) and/or feeding the sensitivity control signals to at least one hardware fault injection detector in the subsystem.

Abstract: A glitch-free low-pass filter circuit includes an integrating circuit, a Schmitt trigger, a first feedback logic circuit and a second feedback logic circuit. The integrating circuit is used to integrate an input signal to generate an integral signal. The Schmitt trigger is used to receive the integral signal to generate a hysteresis signal. The first feedback logic circuit is used to pull the integral signal to a reset voltage or up to the set voltage based on an inverted input signal and an inverted hysteresis signal, wherein the inverted input signal and the inverted hysteresis signal are generated by performing an inversion process. The second feedback logic circuit is used to pull the integral signal down to the reset voltage or up to the set voltage based on the inverted hysteresis signal and an output signal, wherein the output signal is generated by performing the inversion process twice.

Abstract: A monolithic semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a first transistor disposed on the substrate and including the first nitride semiconductor layer and the second nitride semiconductor layer, the first transistor being of a high-electron-mobility transistor (HEMT) type for power amplification; and a first bias circuit disposed on the substrate and including a second transistor of the HEMT type disposed outside a propagation path of a radio-frequency signal inputted to the first transistor, the first bias circuit applying bias voltage to a gate of the first transistor.

Abstract: An embodiment of the present disclosure provides a conversion circuit for converting a single-ended input to a differential input, which has fewer switches and fewer capacitors. This conversion circuit increases the signal-to-noise ratio (SNR), and the conversion circuit directly uses the higher supply voltage AVDD without being bucked by the regulator, wherein the common mode voltage is AVDD/2N, and N is greater than 1. Overall, not only the circuit area is smaller and the SNR is higher, but also the manufacturing cost is reduced. In addition, compared with the prior art, the conversion circuit of the embodiment of the present disclosure has only three operation periods, so the control is simpler and the operation speed is faster.

Abstract: A microcontroller and a memory control method for the microcontroller are provided. The microcontroller includes a memory array, multiple memory controllers, and multiple counting controllers. The memory array includes multiple memory segments. The counting controllers count based on a memory clock to generate count values, respectively. When a count value reaches a preset value, a counting controller corresponding to the count value controls a corresponding memory controller to enter a power saving mode. When receiving an operation command, the counting controller resets the count value and controls the corresponding memory controller to enter an operation mode.

Abstract: A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.

Abstract: An event trigger master coupled to a first peripheral device and including an event receiving interface, a storage element, a state machine, and a master interface is provided. The event receiving interface is configured to receive an event request. The storage element includes a command queue to store a set command. The state machine performs the set command to access the first peripheral device or a second peripheral device in response to the event request being triggered. The master interface is coupled to the state machine, the first peripheral device, and the second peripheral device. The state machine accesses the first or second peripheral device via the master interface.

Abstract: A power storage pack includes: a power storage cell; a power storage tab; a protection circuit substrate; a semiconductor element; and a metal plate for power storage tab joint that is connected to the semiconductor element on the first main surface of the metal plate for power storage tab joint and that includes a portion whose thickness is at most 0.2 mm. The metal plate for power storage tab joint is joined to the power storage tab on the second main surface of the metal plate for power storage tab joint to include an overlap portion in which the power storage tab, the metal plate for power storage tab joint, the semiconductor element, and the protection circuit substrate overlap each other; and there is a portion in which a region that may be the conduction path between the power storage tab and the protection circuit substrate overlaps the overlap portion.

Abstract: A semiconductor device for power amplification includes: a source electrode, a drain electrode, and a gate electrode disposed above a semiconductor stack structure including a first nitride semiconductor layer and a second nitride semiconductor layer; and a source field plate that is disposed above the semiconductor stack structure between the gate electrode and the drain electrode, and has a same potential as a potential of the source electrode. The source field plate has a staircase shape, and even when length LF2 of an upper section is increased for electric field relaxation, an increase in parasitic capacitance Cds generated between the source field plate and a 2DEG surface is inhibited.

Abstract: A hydrogen sensor includes: a first electrode which is planar; a second electrode which is planar, faces the first electrode, and includes an exposed portion; a metal oxide layer which is sandwiched between a surface of the first electrode and a surface of the second electrode, and has a resistance that changes due to hydrogen; and two terminals, i.e., a first terminal and a second terminal, that are connected to the second electrode.