Abstract: A solid-state imaging device includes: pixels disposed in a matrix of pixel rows and pixel columns; control wires provided for the pixel rows or the pixel columns, and each connected to at least two pixels out of the pixels, the at least two pixels being included in one of the pixel rows or the pixel columns for which the control wire is provided; drive circuits that are provided for the control wires, each include buffer elements in at least two stages, and each output a control signal to one of the control wires for which the drive circuit is provided, the buffer elements in the at least two stages being connected in series; and a first wire that short-circuits output wires of the buffer elements in one of the at least two stages in at least two of the plurality of drive circuits.

Abstract: An electronic circuit includes a driving cell, one or more driven cells and one or more inverters. The driving cell has two or more inputs and at least one output and is configured to toggle the output between first and second logic states in response to the inputs. Each driven cell has two or more inputs, of which at least one input is configured to be driven by the output of the driving cell. The one or more inverters are placed in a signal network that connects the driving cell to the driven cells. The inverters are configured to balance, over the signal network, (i) a first capacitive load charged by electrical currents caused by transitions from the first logic state to the second logic state and (ii) a second capacitive load charged by electrical currents caused by transitions from the second logic state to the first logic state.

Abstract: A gas monitoring system includes at least one sensor device that detects gas and outputs a detection result; and a gateway that receives the detection result. The at least one sensor device includes a sensor module having a gas sensor that detects gas; an analog-to-digital (A/D) converter that processes the detection result outputted from the gas sensor; a communication module that communicates with the sensor module and transmits information processed by the A/D converter exteriorly of the at least one sensor device; a power source that is an electric power source of the sensor module; and a power source that is an electric power source of the communication module.

Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.

Abstract: A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.

Abstract: A light-emitting device including: a mounting substrate including a mounting surface; a light-emitting element disposed on the mounting surface; a light transmissive component disposed on the light-emitting element; and a resin component directly contacting and covering a side surface of the light-emitting element and a side surface of the light transmissive component. The resin component includes a peripheral portion that directly contacts and covers the side surface of the light transmissive component, a protrusion that protrudes from the peripheral portion, and a cover portion that directly contacts and covers an outer edge portion of a topmost surface of the light transmissive component. The height from the mounting surface to a top of the cover portion is greater than a height from the mounting surface to the topmost surface of the light transmissive component, and the topmost surface of the light transmissive component includes a region exposed from the resin component.

Abstract: A control circuit including a timer circuit and a voltage monitor circuit is provided. The timer circuit enables a trigger signal every a fixed time interval in response to a wake-up event. The voltage monitor circuit is configured to determine whether the operation voltage reaches the expected voltage and includes a signal-generating circuit, a first delay circuit, a second delay circuit, and a determination circuit. The signal-generating circuit generates a reference signal according to the trigger signal. The first delay circuit receives the operation voltage and delays the reference signal to generate a first delay signal. The second delay circuit delays the trigger signal to generate a second delay signal. The determination circuit enables a wake-up signal according to the reference signal, the first delay signal, and the second delay signal in response to the wake-up event.

Abstract: An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor, one or more of which code instructions including one or more error-detection bits. The protection circuitry is configured to detect an error in the program code using the error-detection bits, and to initiate a responsive action in response to detecting the error.

Abstract: A power consumption evaluation device and a power consumption evaluation method are provided. The power consumption evaluation device includes a power converter, a counter, and a controller. The power converter includes a power switch. The power switch performs a switching operation according to a control signal, so that the power converter supplies power to a corresponding load among at least one load. The counter counts one of a positive pulse and a negative pulse of the control signal during a measurement period to obtain a count value. The controller generates an evaluation result of the corresponding load according to the count value.

Abstract: A reference current/voltage generator includes a current mirror unit and a current-mode temperature compensation unit. The current mirror unit generates a first current, a first sum current and a second sum current flowing through first to third terminals thereof, and the first current, the first sum current and the second sum current are in a multiple relationship. The current-mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and when a voltage on the second terminal is equal to a voltage on the third terminal, the first sum current is a sum of a current proportional to absolute temperature (PTAT) and a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is an output terminal of the reference current/voltage generator and configured to output the first current as a reference current.

Abstract: A distance-measuring imaging device includes a light source that applies light according to timing of a light emission signal; a solid-state imager that performs, for an object, exposure according to timing of an exposure signal, and generates raw data corresponding to an exposure amount of the exposure; a signal amount comparator that determines a magnitude relationship in signal amount in the raw data; and a distance calculator that generates and outputs a distance signal based on a determination result. The solid-state imager accumulates, in each of different signal accumulation regions for accumulating signals detected in a same pixel, a signal by exposure in an exposure period that differs in exposure signal timing. The signal amount comparator determines the magnitude relationship between the signals accumulated in the signal accumulation regions. The distance calculator calculates the distance to the object using an arithmetic expression selected depending on the determination result.

Abstract: A semiconductor device includes: a semiconductor layer in a rectangular shape in a plan view; a transistor provided in a first region; and a drain lead-out region provided in a second region. A border line is a straight line parallel to longer sides of the semiconductor layer. The first region includes a plurality of source pads and gate pads. The second region includes a plurality of drain pads. One gate pad among the gate pads is disposed to dispose none of the plurality of source pads between (i) the one gate pad and (ii) one longer side and one shorter side. One drain pad among the plurality of drain pads is in the same shape as the one gate pad and is disposed close to a second vertex. The plurality of source pads include a source pad that is in a rectangular shape or an obround shape having a longitudinal direction parallel to the longer sides of the semiconductor layer.

Abstract: A control circuit and method for detecting a glitch signal on a bus are provided. The control circuit includes: input ends, respectively receiving a data signal and a clock signal from the bus; a counter, for calculating a time or a number of times in a low level period of the clock signal; a comparator, receiving an output of the time counted by the counter and a threshold value, and generating a comparison result by comparing the time and the threshold value; and an error detector, coupled to the comparator to receive the comparison result, and generating an error flag. When the comparison result indicates that there is a level change during the low level period of the clock signal, the error detector generates an error flag.

Abstract: A power verification circuit is provided. The power verification circuit includes a current source, a resistive random access memory (RRAM) cell and a Zener diode. The current source is coupled to a power terminal. The RRAM cell is coupled between the current source and a ground terminal. The Zener diode has an anode coupled to the RRAM cell and a cathode coupled to the power terminal. The impedance of the RRAM cell is determined by the power voltage applied to the power terminal.

Abstract: An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.

Abstract: A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

Abstract: A voltage measurement device includes: a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a device address generating circuit which generates a device address according to a first address assignment command received from a preceding voltage detection circuit located at a preceding stage; and an address assignment command generating circuit which generates a second address assignment command according to the first address assignment command, and sends the second address assignment command to a next voltage detection circuit located at a next stage.

Abstract: A memory device includes a memory array and a memory controller. The memory array includes a first memory bank, a second memory bank, and a third memory bank. The first memory bank includes a first sub memory bank. The second memory bank includes a second sub memory bank. The memory controller, according to a write command from a host, writes first data from the host to the first memory bank and second data to the second memory bank at the same time, and writes a first Hamming weight of the first data to the third memory bank. The second data is the inverse of the first data.

Abstract: A semiconductor device includes: a mounting board; and a semiconductor element disposed on the mounting board via metal bumps, wherein the semiconductor element includes a semiconductor stacked structure and first electrodes, the mounting board includes second electrodes, the metal bumps include a second layer in contact with the second electrodes of the semiconductor element and a first layer located on a side opposite to the second electrodes, an average crystal grain size of crystals included in the second layer is larger than an average crystal grain size of crystals included in the first layer, and the first layer is spaced apart from the second electrodes of the semiconductor element.

Abstract: An image binarization method and an electronic device using the same are provided. The method includes capturing an image by an image capturing device; selecting a target pixel row arranged at the front from one or more unselected first pixel rows among M pixel rows of the image according to a row order by a binarization circuit; performing, by the binarization circuit, a binarization operation on the target pixel row to obtain a binarized pixel row; storing the binarized pixel row to a main memory by the binarization circuit; performing, by the binarization circuit, the binarization operation to the remaining one or more first pixel rows until M binarized pixel rows are obtained, so as to complete the binarization operation.