Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, an SPI bus, a memory device electrically connected to the master device via the SPI bus, and a plurality of slave devices electrically connected to the master device via the eSPI bus. Each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line. After obtaining program code from the memory device via the master device, a first slave device is configured to decrypt the program code according to a first security code, and transmit the program code decrypted by the first security code to the slave devices via the control line, so that the program code decrypted by the first security code is decrypted in the slave devices according to a decryption sequence.

Abstract: An amplifier circuit has an output stage, a first current source, a second current source, a third current source, a fourth current source, and a voltage clamping voltage. The output stage has a first P-type transistor and a first N-type transistor. The voltage clamping circuit receives a first bias voltage and a second bias voltage, and has a first end and a second end. When a second input current is positive current and the input current is a negative current or a zero current, the first end provides a first clamping voltage greater than the first bias voltage to a gate of the first P-type transistor. When the first input current is positive and the second input current is a negative current or zero current, the second end provides a second clamping voltage lower than the second bias voltage to a gate of the first N-type transistor.

Abstract: In a first vertical field-effect transistor in which first source regions and first connectors each of which electrically connects a first body region and a first source electrode are alternately and periodically disposed in a first direction (Y direction) in which a first trench extends, a ratio of LS [?m] to LB [?m] is at least 1/7 and at most 1/3, where LS denotes a length of one of the first source regions in the first direction, and LB denotes a length of one of the first connectors in the first direction, and LB??0.024×(VGS)2+0.633×VGS?0.721 is satisfied for a voltage VGS [V] of a specification value of a semiconductor device, the voltage VGS being applied to a first gate conductor with reference to an electric potential of the first source electrode.

Abstract: A control circuit driving a display panel and including a transmission interface, a charging circuit, an image driving circuit, and a loading management circuit is provided. The transmission interface is configured to be coupled to the display panel. The charging circuit is configured to charge a capacitor. The image driving circuit transforms the voltage of the capacitor into a plurality of driving signals and provides the driving signals to the display panel via the transmission interface. The loading management circuit measures the charge time of the capacitor. In response to the charge time of the capacitor exceeding a threshold value, the loading management circuit asserts a flag to indicate the occurrence of an overload.

Abstract: A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.

Abstract: A detection circuit for detecting a clock signal includes a multiplexer, a digital-to-analog converter, a comparator, and a counter. The multiplexer outputs either a first signal or a second signal as a selection signal. The digital-to-analog converter outputs a reference voltage according to the selection signal. The comparator compares the clock signal to the reference voltage to generate a comparison signal. The counter counts a reference clock signal to generate an overflow signal, and resets the overflow signal according to the comparison signal. The overflow signal indicates the amplitude of the clock signal.

Abstract: A semiconductor device includes: a first latch circuit that includes a first inverting circuit, a second inverting circuit, a third inverting circuit, and a fourth inverting circuit; a first first-type well region; a second first-type well region; and a second-type well region. In a plan view, a distance between a drain of a first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the third inverting circuit is longer than a distance between the drain of the first-type MOS transistor in the first inverting circuit and a drain of a first-type MOS transistor in the fourth inverting circuit.

Abstract: A semiconductor laser element includes: an n-type cladding layer disposed above an n-type semiconductor substrate (a chip-like substrate); an active layer disposed above the n-type cladding layer; and a p-type cladding layer disposed above the active layer, in which the active layer includes a well layer and a barrier layer, an energy band gap of the barrier layer is larger than an energy band gap of the n-type cladding layer, and a refractive index of the barrier layer is higher than a refractive index of the n-type cladding layer.

Abstract: A solid-state imaging device includes: a plurality of pixel cells arranged in a matrix. In the solid-state imaging device, each of the plurality of pixel cells includes: a photoelectric converter that generates charge by photoelectric conversion, and holds a potential according to an amount of the charge generated; an initializer that initializes the potential of the photoelectric converter; a comparison section that compares the potential of the photoelectric converter and a predetermined reference signal, and causes the initializer to perform initialization when the potential of the photoelectric converter and the predetermined reference signal match; and a counter that counts a total number of times of initialization performed by the initializer, and outputs a signal corresponding to the total number of times as a first signal indicating an intensity of incident light.

Abstract: A supply voltage detecting circuit has a voltage detection circuit and a current clamping circuit. The voltage detection circuit receives and detects a supply voltage and is used to detect to generate a low-voltage detection signal. When the supply voltage is lower than a set level, the low voltage detection signal output by the voltage detection circuit turns off the current clamping circuit, and a transistor current flowing through the voltage detection circuit is proportional to the supply voltage; and when the supply voltage is higher than or equal to the set level, the low voltage detection signal output by the voltage detection circuit turns on the current clamping circuit, and the current clamping circuit provides a constant current to maintain the operation of the voltage detection circuit, wherein the transistor current flowing through the voltage detection circuit is proportional to the constant current.

Abstract: The present disclosure relates to a low-dropout regulator that limits a quiescent current. It mainly includes an error amplifier, an output switching transistor, a feedback switching transistor, a current duplicating circuit, and a clamping current source. The clamping current source is added between an input voltage and the feedback switching transistor, so that a feedback current outputted by the feedback switching transistor is clamped, and the highest value is only proportional to a current value of the clamping current source. In this way, the quiescent current outputted by the low-dropout regulator is no longer increasing indefinitely in proportional to a load current, which can effectively solve the technical problems of poor stability and decreased efficiency caused by the infinite increase of the quiescent current.

Abstract: An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.

Abstract: An IC is provided. The IC includes an input pin, a controller, a timer, a first memory, a processor, at least one output pin, an output module coupled to the output pin, and a direct memory access (DMA) device coupled between the output module and the first memory. The controller is configured to provide a first control signal in response to a command from the input pin. The timer is configured to periodically provide a trigger signal according to the first control signal. The processor is configured to store first data in the first memory. The DMA device is configured to obtain the first data from the first memory in response to the trigger signal, and transmit the first data to the output module. The output module is configured to provide the first data to the output pin according to a transmission rate.

Abstract: A system on chip including a first master circuit, a second master circuit, a routing circuit, a bridge control circuit, and a peripheral circuit is provided. The first master circuit provides a first command. The second master circuit provides a second command. The routing circuit receives the first command and the second command and provides an output command. The bridge control circuit receives the output command and stores an attribute setting value. In response to the routing circuit receiving the first command and the first command pointing to the peripheral circuit, the routing circuit uses the first command as the output command and the bridge control circuit determines whether attribute information of the output command matches the attribute setting value. In response to the attribute information of the output command matching the attribute setting value, the bridge control circuit provides the output command to the peripheral circuit.

Abstract: A microcontroller and a memory control method for the microcontroller are provided. The microcontroller includes a memory array, multiple memory controllers, and multiple counting controllers. The memory array includes multiple memory segments. The counting controllers count based on a memory clock to generate count values, respectively. When a count value reaches a preset value, a counting controller corresponding to the count value controls a corresponding memory controller to enter a power saving mode. When receiving an operation command, the counting controller resets the count value and controls the corresponding memory controller to enter an operation mode.

Abstract: A motor control device and a motor control method are provided. The motor control device includes a memory and a controller. During an initialization period, the controller drives a brushless DC motor to change a rotor position through a drive circuit for adjusting and obtaining a starting angle and a locked exciting current corresponding to the starting angle, and the controller stores starting-angle information corresponding to the starting angle and locked exciting-current information corresponding to the locked exciting current in the memory. After the initialization period ends, during a normal rotation period, the controller maintains the rotor position of the brushless DC motor at the starting angle with the locked exciting current through the drive circuit, until the controller activates the brushless DC motor through the drive circuit.

Abstract: A voltage measurement device is a voltage measurement device including a plurality of voltage detection circuits which measure cell voltages of a plurality of cells connected in series. Each of the plurality of voltage detection circuits includes: a communication end information holding circuit which holds communication end information specifying, as at least one communication end position, at least one of the plurality of voltage detection circuits; and a communication control circuit which controls transfer for sending a communication command received from a preceding voltage detection circuit located at a preceding stage to a next voltage detection circuit located at a next stage, according to the communication end information.

Abstract: A solid-state imaging apparatus includes pixel cells arranged in a matrix. Each pixel cell includes: a first photodiode that accumulates a signal charge generated by photoelectric conversion; a second photodiode that functions as a first holder that holds a signal charge that overflows from the first photodiode; a second holder; and a first transfer transistor that transfers the signal charge held in the second photodiode to the second holder.

Abstract: A sensor is provided and is disposed on a package body of an integrated circuit chip. The sensor includes a sensing element, a protective element, a cover, and at least two traces. The sensing element is disposed on the integrated circuit chip. The protective element is disposed on the integrated circuit chip and surrounds the sensing element. The cover is connected to the protective element. The at least two traces are electrically connected to the sensing element and to at least two pins of the integrated circuit chip.

Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.