Abstract: A puncture forming method is a method of forming punctures in a sample by irradiating a surface of the sample with a light beam. The puncture forming method includes: forming a first puncture by irradiating a first position on the surface of the sample with a first pulse of the light beam; and after the forming of the first puncture, forming a second puncture which at least partially overlaps the first puncture by irradiating, with a second pulse of the light beam, a second position on the surface of the sample positioned away from the first position in a first direction. The second puncture has a tip which is positioned inside the sample and which is bent in a direction opposite to the first direction.

Abstract: A battery monitoring device includes: a pair of terminals for measuring voltage or current of a battery, and to which a filter unit including a capacitive element is connected; an AD converter that measures a waveform of voltage between the terminals during charging or discharging of the capacitive element; and a time constant calculation unit that calculates a time constant of the filter unit based on the waveform measured. The AD converter is, for example, a first AD converter or a second AD converter. The filter unit is, for example, a first filter unit or a second filter unit.

Abstract: A comparator testing circuit and a testing method are provided. The comparator testing circuit includes a switching circuit, a comparator, and a determination circuit. The switching circuit receives a first signal, a second signal, and a switching signal, and outputs one of the first signal and the second signal as a first input signal and the other of the first signal and the second signal as a second input signal according to the switching signal. The comparator compares the first input signal with the second input signal to generate an output signal. The determination circuit determines whether the comparator is abnormal based on the switching signal and the output signal to generate an exception flag.

Abstract: A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

Abstract: A solid-state imaging device includes: a photoelectric conversion element that is disposed on a semiconductor substrate and generates signal charges by photoelectric conversion; a first diffusion layer that holds signal charges transferred from the photoelectric conversion element; a capacitive element that holds signal charges overflowing from the photoelectric conversion element; an amplifier transistor that outputs a signal according to the signal charges in the first diffusion layer; a first contact that is connected to the first diffusion layer; a second contact that is connected to a gate of the amplifier transistor; and a first wire that connects the first contact and the second contact. A shortest distance between the semiconductor substrate and the first wire is less than a shortest distance between the semiconductor substrate and the capacitive element.

Abstract: An electronic device includes a first memory controller, a second memory controller, and a memory access controller. The first memory controller stores setting information of a predetermined memory, wherein the predetermined memory is defined as an execute-only-memory. The second memory controller provides and sets an enabling register according to the setting information of the predetermined memory, and generates an enabling signal. The memory access controller accesses the first memory controller and the second memory controller to move the data of the predetermined memory to a predetermined memory space corresponding to the enabling register according to the enabling signal and the setting information of the predetermined memory.

Abstract: A memory device includes a main memory, a first sub-memory and a controller. When the first sub-memory is erased, the first sub-memory generates a first erase completion signal. The controller receives an erase signal to erase the main memory. The controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.

Abstract: A radio-frequency power amplifier device includes: a carrier amplifier semiconductor device and a peak amplifier semiconductor device on a multilayer submount substrate; a bias power supply semiconductor device; second radio-frequency signal wiring that transmits a radio-frequency signal to the carrier amplifier semiconductor device and the peak amplifier semiconductor device; and carrier-amplifier bias power supply wiring that is wired in a third wiring layer and supplies a bias power supply voltage. The second radio-frequency signal wiring and the carrier-amplifier bias power supply wiring intersect in a plan view. The radio-frequency power amplifier device includes: a shield pattern that is located in a second wiring layer between a first wiring layer and the third wiring layer; and one or more connection vias disposed in an extension direction of the carrier-amplifier bias power supply wiring. The one or more connection vias are connected to the shield pattern.

Abstract: A system includes a memory and a processor. The memory is configured to store a machine learning (ML) model. The processor is configured to (i) obtain a set of training audio signals that are labeled with respective levels of distortion, (ii) convert the training audio signals into respective images, (iii) train the ML model to estimate the levels of the distortion based on the images, (iv) receive an input audio signal, (v) convert the input audio signal into an image, and (vi) estimate a level of the distortion in the input audio signal, by applying the trained ML model to the image.

Abstract: A memory device and an operating method thereof are provided. The memory device includes a memory controller, an address transforming circuit, and a memory array. The memory controller generates a programming address among multiple candidate programming addresses according to an application. The address transforming circuit stores multiple physical address data and multiple mask data. The physical address data respectively correspond to the candidate programming addresses. The address transforming circuit executes a first logical calculation according to the programming address, the physical address data, and the mask data to generate a physical address. The memory controller executes an access operation on the memory array according to the physical address.

Abstract: A battery management circuit includes: a reference signal generator that generates a first reference frequency signal and a second reference frequency signal having a phase different from a phase of the first reference frequency signal; an alternating-current superimposer that superimposes an alternating current on the secondary battery, the alternating current having a frequency component of the first reference frequency signal; a voltage measurer that measures a voltage of the secondary battery by performing sampling using a frequency; a current measurer that measures a current of the secondary battery by performing sampling using a frequency; and a converter that converts each of results of measurements by the voltage measurer and the current measurer into a complex voltage and a complex current, by multiplying the result of the measurement by the first reference frequency signal and the second reference frequency signal.

Abstract: A gas sensor includes: a gas-sensitive body layer disposed above a substrate and including a metal oxide layer; a first electrode on the gas-sensitive body layer; and a second electrode on the gas-sensitive body layer, being apart from the first electrode by a gap. The gas-sensitive body layer has a resistance change characteristic that reversibly transitions to a high-resistance state and a low-resistance state on basis of a voltage applied across the first electrode and the second electrode. At least a part of the gas-sensitive body layer is exposed to the gap. The gas-sensitive body layer has a resistance that decreases when gas containing a hydrogen atom is in contact with the second electrode.

Abstract: A white light emitting device includes: first light-emitting units to which a first current is applied; and second light-emitting units to which a second current which is different from the first current is applied. When the first current is applied to the first light-emitting units and the second current is applied to the second light-emitting units, an average emission chromaticity of the first light-emitting units and an average emission chromaticity of the second light-emitting units are identical colors. When the same current is applied to both the first light-emitting units and the second light-emitting units, the average emission chromaticity of the first light-emitting units and the average emission chromaticity of the second light-emitting units are non-identical colors.

Abstract: An electronic device includes a controller, a clock generator, a first operation interface and a first functional unit. The controller generates a first clock enable signal, and then generates a first operation instruction. The clock generator generates a first clock according to the first clock enable signal. The first operation interface generates a first power supply signal according to the first clock, and translates the first operation instruction into a first operation signal. The first functional unit is enabled according to the first power supply signal, and starts to operate according to the first operation signal.

Abstract: A method of speeding up a secure boot process and an electronic device using the method. The method includes the following. Whether a storage medium stores a pre-stored hash value corresponding to an image file for the secure boot process is determined. A hash value of the image file is calculated to determine whether the hash value matches the pre-stored hash value in response to the storage medium storing the pre-stored hash value. Firmware in the image file is executed to boot up the electronic device in response to the hash value matching the pre-stored hash value.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.

Abstract: A controller used in a computing device executes the following steps. When a security profile stored in a storage device is successfully verified, according to a security profile configuration stored in the controller, an operation mode described in the security profile is used. When the used operation mode is in a non-secure mode, the booting of the computer device is directly completed. When the used operation mode is a secure mode and a main BIOS of the computing device is not valid, at least one BIOS stored in the storage device is used to recover the main BIOS, and the computer device is rebooted. When the used operation mode is a secure mode and the main BIOS is valid, but the storage device does not store the main BIOS, the main BIOS is backed up and to be stored in the storage device.

Abstract: A distance information acquisition device includes: a light emitter which emits light according to an emission pulse indicating emission; a solid-state imaging element which performs exposure according to an exposure pulse indicating exposure; an emission/exposure controller which generates a timing signal indicating a plurality of pairs of the emission pulse and the exposure pulse having a time difference that is different in each of the plurality of pairs; and a multipath detector which obtains a sequence of received light signals from the solid-state imaging element by the emission and the exposure that correspond to each of the plurality of pairs, compares the obtained sequence of received light signals and reference data created in advance as a model of a sequence of received light signals in a multipath-free environment, and determines the presence or absence of multipath according to a difference in a comparison result.

Abstract: A monitoring system includes an arithmetic processor. The arithmetic processor receives captured image information representing a captured image obtained by capturing an image of a subject and generates notification information representing a particular notification content depending on a condition of the subject. The arithmetic processor includes a first arithmetic processor and a second arithmetic processor. The first arithmetic processor obtains a condition quantity by quantifying the condition of the subject by reference to the captured image information and based on a parameter about a human activity status. The second arithmetic processor selects, according to the condition quantity, the particular notification content from contents of notification classified into N stages, where N is an integer equal to or greater than three.

Abstract: A face-down mountable chip-size package semiconductor device includes a semiconductor layer and N (N is an integer greater than or equal to three) vertical MOS transistors in the semiconductor layer. Each of the N vertical MOS transistors includes, on an upper surface of the semiconductor layer, a gate pad electrically connected to a gate electrode of the vertical MOS transistor and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer includes a semiconductor substrate. The semiconductor substrate functions as a common drain region for the N vertical MOS transistors. For each of the N vertical MOS transistors, a surface area of the vertical MOS transistor in a plan view of the semiconductor layer increases with an increase in a maximum specified current of the vertical MOS transistor.