Patents Assigned to NVIDIA Corp.
  • CIRCUIT STRUCTURES TO MEASURE FLIP-FLOP TIMING CHARACTERISTICS
    Publication number: 20230275572
    Abstract: A ring oscillator circuit with a frequency that is sensitive to the timing of a clock-to-Q (clk2Q) propagation delay of one or more flip-flops utilized in the ring oscillator. The clock2Q is the delay between the clock signal arriving at the clock pin on the flop and the Q output reflecting the state of the input data signal to the flop. Clk2q delay measurements are made based on measurement of the ring oscillator frequency, leading to more accurate estimates of clk2Q for different types of flip-flops and flip-flop combinations, which may in turn enable improvements in circuit layouts, performance, and area.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 31, 2023
    Applicant: NVIDIA Corp.
    Inventors: Tezaswi Raja, Prashant Singh
  • Adaptive Pixel Sampling Order for Temporally Dense Rendering
    Publication number: 20230269391
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Application
    Filed: March 15, 2023
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • CMOS SIGNALING FRONT END FOR EXTRA SHORT REACH LINKS
    Publication number: 20230269119
    Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
    Type: Application
    Filed: March 10, 2023
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Sanquan Song, John Poulton
  • KEEPER-FREE VOLATILE MEMORY SYSTEM
    Publication number: 20230267992
    Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 24, 2023
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Stefan P. Sywyk, Andreas Jon Gotterba, Jesse Wang
  • TRANSCEIVER SYSTEM WITH END-TO-END RELIABILITY AND ORDERING PROTOCOLS
    Publication number: 20230261794
    Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.
    Type: Application
    Filed: February 17, 2022
    Publication date: August 17, 2023
    Applicant: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison, John Martin Snyder
  • Simultaneous Bi-directional Hybrid Transceiver for Single-Ended Voltage Mode Signaling
    Publication number: 20230246661
    Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
    Type: Application
    Filed: September 12, 2022
    Publication date: August 3, 2023
    Applicant: NVIDIA Corp.
    Inventors: Xi Chen, Yoshinori Nishi, John Poulton
  • Layout Parasitics and Device Parameter Prediction using Graph Neural Networks
    Publication number: 20230237313
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Application
    Filed: April 3, 2023
    Publication date: July 27, 2023
    Applicant: NVIDIA Corp.
    Inventors: Haoxing Ren, George Ferenc Kokai, Ting Ku, Walker Joseph Turner
  • Current flattening circuit for protection against power side channel attacks
    Patent number: 11687679
    Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: June 27, 2023
    Assignee: NVIDIA CORP.
    Inventors: Nikola Nedovic, Sudhir Shrikantha Kudva
  • Staggered Dual-Side Multi-Chip Interconnect
    Publication number: 20230197696
    Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • SLEW SIGNAL SHAPER CIRCUIT
    Publication number: 20230197127
    Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.
    Type: Application
    Filed: December 20, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Lalit Gupta, Andreas Jon Gotterba, Jesse Wang
  • Layout parasitics and device parameter prediction using graph neural networks
    Patent number: 11651194
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: May 16, 2023
    Assignee: NVIDIA Corp.
    Inventors: Haoxing Ren, George Kokai, Ting Ku, Walker Joseph Turner
  • IR drop prediction with maximum convolutional neural network
    Patent number: 11645533
    Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: May 9, 2023
    Assignee: NVIDIA Corp.
    Inventors: Zhiyao Xie, Haoxing Ren, Brucek Khailany, Sheng Ye
  • Adaptive pixel sampling order for temporally dense rendering
    Patent number: 11638028
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 25, 2023
    Assignee: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • Foveation and spatial hashing in layer-based computer-generated holograms
    Patent number: 11635623
    Abstract: The computational scaling challenges of holographic displays are mitigated by techniques for generating holograms that introduce foveation into a wave front recording planes approach to hologram generation. Spatial hashing is applied to organize the points or polygons of a display object into keys and values.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 25, 2023
    Assignee: Nvidia Corp.
    Inventors: Jui-Hsien Wang, Ward Lopes, Rachel Anastasia Brown, Peter Shirley
  • Foveated display for augmented reality
    Patent number: 11630312
    Abstract: An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: April 18, 2023
    Assignee: NVIDIA Corp.
    Inventors: Jonghyun Kim, Youngmo Jeong, Michael Stengel, Morgan McGuire, David Luebke
  • CMOS signaling front end for extra short reach links
    Patent number: 11632275
    Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: April 18, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sanquan Song, John Poulton
  • SOFTWARE-DIRECTED DIVERGENT BRANCH TARGET PRIORITIZATION
    Publication number: 20230115044
    Abstract: Instruction set architecture extensions to configure priority ordering of divergent target branch instructions on SIMT computing platforms to enable tools such as compilers (e.g., under influence of execution profilers) or human software developers to configure branch direction prioritization explicitly in code. Extensions for simple (two-way) branch instructions as well as multi-target (more than two branch target instructions) are disclosed.
    Type: Application
    Filed: January 4, 2022
    Publication date: April 13, 2023
    Applicant: NVIDIA Corp.
    Inventors: Sana Damani, Sean Treichler, Mark Stephenson, Daniel Robert Johnson
  • Semiconductor assembly
    Patent number: 11616019
    Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 28, 2023
    Assignee: NVIDIA Corp.
    Inventors: Jacky Qiu, Martin Ding, Jerry Zhou, Minto Zheng
  • ADVERSARIAL SCENARIOS FOR SAFETY TESTING OF AUTONOMOUS VEHICLES
    Publication number: 20230079196
    Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Applicant: NVIDIA Corp.
    Inventors: Siva Kumar Sastry Hari, Iuri Frosio, Zahra Ghodsi, Anima Anandkumar, Timothy Tsai, Stephen W. Keckler, Alejandro Troccoli
  • Techniques to improve current regulator capability to protect the secured circuit from power side channel attack
    Patent number: 11594962
    Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 28, 2023
    Assignee: NVIDIA CORP.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Sanquan Song