Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: An encoding process for bus data utilizes data from multiple data line groups on a multi-byte wide bus where each group has an associated DBI line. The process leverages the expanded encoding space for the multiple groups and associated multiple DBI bits. This process may be expanded to four bytes, eight bytes, etc.

Abstract: A PAM signaling system utilizes multiple equalizers on each data lane of a serial data bus, each of the equalizers associated with a different signal eye of the serial data bus.

Abstract: A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.

Abstract: Methods of operating a serial data bus generate two-level bridge symbols to insert between four-level symbols on one or more data lanes of the serial data bus, to reduce voltage deltas on the one or more data lanes during data transmission on the serial data bus.

Abstract: A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.

Abstract: A circuit includes a splitter to extract L bits from each of a plurality of N-bit transmissions on a data bus, a decoder to generate output data comprising N-L bits of each N-bit transmission, and a delay circuit to apply the L bits for a previous transmission to control the inversion of a current transmission at the decoder.

Abstract: An image processing method extracts consecutive input blurry frames from a video, and generates sharp frames corresponding to the input blurry frames. An optical flow is determined between the sharp frames, and the optical flow is used to compute a per-pixel blur kernel. The blur kernel is used to reblur each of the sharp frames into a corresponding re-blurred frame. The re-blurred frame is used to fine-tune the deblur network by minimizing the distance between the re-blurred frame and the input blurry frame.

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.