Patents Assigned to NVIDIA Corp.
  • AVERAGE POWER ESTIMATION USING GRAPH NEURAL NETWORKS
    Publication number: 20210158155
    Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.
    Type: Application
    Filed: August 13, 2020
    Publication date: May 27, 2021
    Applicant: NVIDIA Corp.
    Inventors: Yanqing Zhang, Haoxing Ren, Brucek Khailany
  • Deep learning based identification of difficult to test nodes
    Patent number: 11010516
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Data Recovery Technique for Time Interleaved Receiver in Presence of Transmitter Pulse Width Distortion
    Publication number: 20210143824
    Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.
    Type: Application
    Filed: July 30, 2020
    Publication date: May 13, 2021
    Applicant: NVIDIA Corp.
    Inventors: Gaurawa Kumar, Ky-Anh Tran, Olakanmi Oluwole, Vishnu Balan
  • Reference noise compensation for single-ended signaling
    Patent number: 10999051
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 4, 2021
    Assignee: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
    Publication number: 20210124558
    Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.
    Type: Application
    Filed: February 27, 2020
    Publication date: April 29, 2021
    Applicant: NVIDIA Corp.
    Inventors: Ilyas Elkin, Ge Yang, Xi Zhang
  • FULL ADDER CELL WITH IMPROVED POWER EFFICIENCY
    Publication number: 20210124559
    Abstract: This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.
    Type: Application
    Filed: October 23, 2019
    Publication date: April 29, 2021
    Applicant: NVIDIA Corp.
    Inventors: Ilyas Elkin, Ge Yang, Xi Zhang
  • Connectionless fast method for configuring Wi-Fi on displayless Wi-Fi IoT device
    Patent number: 10993110
    Abstract: A method involves a headless IoT device wirelessly communicating a MAC address to a client device in response to a scan by the client device, and receiving from the client device a vendor action frame comprising access credentials for communicating via a Wi-Fi access point. The IoT device applies the credentials to authenticate to the Wi-Fi access point, forms an application layer for communicating over the Wi-Fi access point network, and communicates with the client device via the application layer.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 27, 2021
    Assignee: NVIDIA Corp.
    Inventors: Nagaraj Annaiah, Om Prakash Singh
  • Addressing cache slices in a last level cache
    Patent number: 10983919
    Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 20, 2021
    Assignee: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M Van Dyke, Kun Fang
  • Codebook to reduce error growth arising from channel errors
    Patent number: 10979176
    Abstract: Techniques for limiting the growth of errors in decoded data words that arise from bit errors incurred during transmission. The growth of 3+ bit errors in the decoded data word is limited at the expense of a higher number of two bit errors, which are correctable using practical error correcting codes.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 13, 2021
    Assignee: NVIDIA Corp.
    Inventors: Sunil Sudhakaran, Rohit Rathi
  • Reference noise compensation for single-ended signaling
    Patent number: 10965440
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 30, 2021
    Assignee: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • ADDRESSING CACHE SLICES IN A LAST LEVEL CACHE
    Publication number: 20210089465
    Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Applicant: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang
  • DRIVER GAZE TRACKING SYSTEM FOR USE IN VEHICLES
    Publication number: 20210088784
    Abstract: A gaze tracking system for use by the driver of a vehicle includes an opaque frame circumferentially enclosing a transparent field of view of the driver, light emitting diodes coupled to the opaque frame for emitting infrared light onto various regions of the driver's eye gazing through the transparent field of view, and diodes for sensing intensity of infrared light reflected off of various regions of the driver's eye.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Nvidia Corp.
    Inventors: Eric Whitmire, Kaan Aksit, Michael Stengel, Jan Kautz, David Luebke, Ben Boudaoud
  • Package level power gating
    Patent number: 10957651
    Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 23, 2021
    Assignee: NVIDIA Corp.
    Inventors: Don Templeton, Luke Young Chang, Narayan Kulshrestha
  • REFERENCE NOISE COMPENSATION FOR SINGLE-ENDED SIGNALING
    Publication number: 20210083836
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.
    Type: Application
    Filed: June 18, 2020
    Publication date: March 18, 2021
    Applicant: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G. Tell
  • Reference Noise Compensation for Single-Ended Signaling
    Publication number: 20210083837
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
    Type: Application
    Filed: July 13, 2020
    Publication date: March 18, 2021
    Applicant: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • PACKAGE LEVEL POWER GATING
    Publication number: 20210043574
    Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 11, 2021
    Applicant: NVIDIA Corp.
    Inventors: Don Templeton, Luke Young Chang, Narayan Kulshrestha
  • On-chip execution of in-system test utilizing a generalized test image
    Patent number: 10890620
    Abstract: Systems and methods enable the updating of tests, test sequences, fault models, and test conditions such as voltage and clock frequencies, over the life cycle of a safety critical application for complex integrated circuits and systems.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 12, 2021
    Assignee: NVIDIA Corp.
    Inventors: Milind Bhaiyyasaheb Sonawane, Shantanu K. Sarangi, Sailendra Chadalavada, Sumit Raj, Rangavajjula Kameswara Naga Mahesh, Jayesh Kumar Pandey, Venkat Abilash Reddy Nerallapally
  • OPTIMIZING SOFTWARE-DIRECTED INSTRUCTION REPLICATION FOR GPU ERROR DETECTION
    Publication number: 20210004235
    Abstract: A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: NVIDIA Corp.
    Inventors: Siva Kumar Sastry Hari, Michael Sullivan, Timothy Tsai, Stephen W. Keckler
  • SCALABLE LIGHT-WEIGHT PROTOCOLS FOR WIRE-SPEED PACKET ORDERING
    Publication number: 20200374594
    Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 26, 2020
    Applicant: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison
  • SCALABLE LIGHT-WEIGHT PROTOCOLS FOR WIRE-SPEED PACKET ORDERING
    Publication number: 20200374593
    Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 26, 2020
    Applicant: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison