Patents Assigned to NVIDIA Corp.
  • Low area voltage regulator with feedforward noise cancellation of package resonance
    Patent number: 10845834
    Abstract: A linear regulator for applications with low area constraint resulting in limited load decoupling capacitance that introduces a compensating zero in the regulator loop to counteract the loss of phase margin and further introduces a feed-forward noise cancellation path operating over a wide frequency range covering a first package resonance frequency. The feed-forward path has low power consumption and improves the power-supply rejection ratio.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: November 24, 2020
    Assignee: NVIDIA Corp.
    Inventors: Nikola Nedovic, Sanquan Song
  • Gaze tracking system for use in head mounted displays
    Patent number: 10838492
    Abstract: A gaze tracking system for use in head mounted displays includes an eyepiece having an opaque frame circumferentially enclosing a transparent field of view, light emitting diodes coupled to the opaque frame for emitting infrared light onto various regions of an eye gazing through the transparent field of view, and diodes for sensing intensity of infrared light reflected off of various regions of the eye.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 17, 2020
    Assignee: NVIDIA Corp.
    Inventors: Eric Whitmire, Kaan Aksit, Michael Stengel, Jan Kautz, David Luebke, Ben Boudaoud
  • Data recovery technique for time interleaved receiver in presence of transmitter pulse width distortion
    Patent number: 10833681
    Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 10, 2020
    Assignee: NVIDIA Corp.
    Inventors: Gaurawa Kumar, Ky-Anh Tran, Olakanmi Oluwole, Vishnu Balan
  • Optimizing software-directed instruction replication for GPU error detection
    Patent number: 10817289
    Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 27, 2020
    Assignee: NVIDIA Corp.
    Inventors: Siva Hari, Michael Sullivan, Timothy Tsai, Stephen W. Keckler, Abdulrahman Mahmoud
  • Scalable light-weight protocols for wire-speed packet ordering
    Patent number: 10820057
    Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: October 27, 2020
    Assignee: NVIDIA Corp.
    Inventors: Hans Eberle, Larry Robert Dennison
  • CLOCK DATA RECOVERY CONVERGENCE USING SIGNED TIMING INJECTION
    Publication number: 20200336286
    Abstract: A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.
    Type: Application
    Filed: February 26, 2020
    Publication date: October 22, 2020
    Applicant: NVIDIA Corp.
    Inventors: Pervez Mirza Aziz, Vishnu Balan, Viswanath Annampedu
  • Spatio-temporal image metric for rendered animations
    Patent number: 10810455
    Abstract: An image processing method transforms image sequences into luminances, filters the luminances, determines the temporal differences between the luminances, performs a frequency domain transformation on the temporal differences, and applies a temporal contrast sensitivity function envelope integral to the frequency transform output to generate a temporal image metric. The temporal image metric may be applied for example to train a neural network or to configure a display device to depict a visual indication of the temporal image metric.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 20, 2020
    Assignee: NVIDIA Corp.
    Inventors: Jim Nilsson, Tomas Akenine-Moller
  • IR DROP PREDICTION WITH MAXIMUM CONVOLUTIONAL NEURAL NETWORK
    Publication number: 20200327417
    Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.
    Type: Application
    Filed: March 17, 2020
    Publication date: October 15, 2020
    Applicant: NVIDIA Corp.
    Inventors: Zhiyao Xie, Haoxing Ren, Brucek Khailany, Sheng Ye
  • RECONSTRUCTION FOR TEMPORALLY DENSE RAY TRACE RENDERING
    Publication number: 20200312010
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern. Subframes generated based on the sampling order are communicated over a bus along with motion vectors for tiles of the subframes.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Applicant: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Tomas Guy Akenine-Möller, Jim Nilsson, Marco Salvi, Josef Spjut
  • Adaptive Pixel Sampling Order for Temporally Dense Rendering
    Publication number: 20200314442
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 1, 2020
    Applicant: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • Superpixel sampling networks
    Patent number: 10789678
    Abstract: A superpixel sampling network utilizes a neural network coupled to a differentiable simple linear iterative clustering component to determine pixel-superpixel associations from a set of pixel features output by the neural network. The superpixel sampling network computes updated superpixel centers and final pixel-superpixel associations over a number of iterations.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: September 29, 2020
    Assignee: NVIDIA Corp.
    Inventors: Varun Jampani, Deqing Sun, Ming-Yu Liu, Jan Kautz
  • EFFICIENT NEURAL NETWORK ACCELERATOR DATAFLOWS
    Publication number: 20200293867
    Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture includes multiple chips, each with a central processing element, a global memory buffer, and a plurality of additional processing elements. Each additional processing element includes a weight buffer, an activation buffer, and vector multiply-accumulate units to combine, in parallel, the weight values and the activation values using stationary data flows.
    Type: Application
    Filed: November 4, 2019
    Publication date: September 17, 2020
    Applicant: NVIDIA Corp.
    Inventors: Yakun Shao, Rangharajan Venkatesan, Miaorong Wang, Daniel Smith, William James Dally, Joel Emer, Stephen W. Keckler, Brucek Khailany
  • SWITCHED LOW-DROPOUT VOLTAGE REGULATOR
    Publication number: 20200264642
    Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 20, 2020
    Applicant: NVIDIA Corp.
    Inventors: Sudhir Kudva, John Wilson
  • Field adaptable in-system test mechanisms
    Patent number: 10746798
    Abstract: A system for testing complex integrated circuits in the field using updated tests, test sequences, models, and test conditions such as voltage and clock frequencies, over the life cycle of the circuit.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: August 18, 2020
    Assignee: NVIDIA Corp.
    Inventors: Sailendra Chadalavada, Shantanu K. Sarangi, Milind Bhaiyyasaheb Sonawane, Sunil Bhavsar, Jue Wu, Bonita Bhaskaran, Venkat Abilash Reddy Nerallapally, Badrinath Srirangam
  • Voltage-follower based cross-coupling oscillators with embedded phase-interpolation function
    Patent number: 10742224
    Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: August 11, 2020
    Assignee: NVIDIA Corp.
    Inventors: Xi Chen, Sanquan Song
  • SYSTEM AND METHODS FOR HARDWARE-SOFTWARE COOPERATIVE PIPELINE ERROR DETECTION
    Publication number: 20200210276
    Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
    Type: Application
    Filed: March 6, 2020
    Publication date: July 2, 2020
    Applicant: NVIDIA Corp.
    Inventors: Michael Sullivan, Siva Hari, Brian Zimmer, Timothy Tsai, Stephen W. Keckler
  • Clock data recovery convergence using signed timing injection
    Patent number: 10700846
    Abstract: A system for data and clock recovery includes a timing error detector, a phase detector, and a phase increment injector. The phase increment injector may be used to determine an increment to affect an output of the phase detector or a clocking element. A sign of the increment is determined from a sign or direction of an accumulated version of a clock and data recovery gradient value.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: June 30, 2020
    Assignee: NVIDIA Corp.
    Inventors: Pervez Mirza Aziz, Vishnu Balan, Viswanath Annampedu
  • Computational blur for varifocal displays
    Patent number: 10699383
    Abstract: Methods are disclosed herein to blur an image to be displayed on a stereo display (such as virtual or augmented reality displays) based on the focus and convergence of the user. The methods approximate the complex effect of chromatic aberration on focus, utilizing three (R/G/B) simple Gaussian blurs. For transparency the methods utilize buffers for levels of blur rather than depth. The methods enable real-time chromatic-based blurring effects for VR/AR displays.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: June 30, 2020
    Assignee: NVIDIA Corp.
    Inventors: Morgan McGuire, Kaan Aksit, Pete Shirley, David Luebke
  • USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES
    Publication number: 20200177521
    Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 4, 2020
    Applicant: NVIDIA Corp.
    Inventors: Matthias Augustin Blumrich, Nan Jiang, Larry Robert Dennison
  • Method and apparatus to access high volume test data over high speed interfaces
    Patent number: 10663515
    Abstract: A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: May 26, 2020
    Assignee: NVIDIA Corp.
    Inventors: Kaushik Narayanun, Shantanu Sarangi