Patents Assigned to NVIDIA Corp.
  • Full adder cell with improved power efficiency
    Patent number: 11169779
    Abstract: An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 9, 2021
    Assignee: NVIDIA Corp.
    Inventors: Ilyas Elkin, Ge Yang, Xi Zhang
  • FOVEATED DISPLAY FOR AUGMENTED REALITY
    Publication number: 20210341741
    Abstract: An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 4, 2021
    Applicant: NVIDIA Corp.
    Inventors: Jonghyun Kim, Youngmo Jeong, Michael Stengel, Morgan McGuire, David Luebke
  • USE OF STASHING BUFFERS TO IMPROVE THE EFFICIENCY OF CROSSBAR SWITCHES
    Publication number: 20210344616
    Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Applicant: NVIDIA Corp.
    Inventors: Matthias Augustin Blumrich, Nan Jiang, Larry Robert Dennison
  • Adaptive Pixel Sampling Order for Temporally Dense Rendering
    Publication number: 20210344944
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Application
    Filed: July 6, 2021
    Publication date: November 4, 2021
    Applicant: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • CURRENT FLATTENING CIRCUIT FOR PROTECTION AGAINST POWER SIDE CHANNEL ATTACKS
    Publication number: 20210334411
    Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 28, 2021
    Applicant: NVIDIA Corp.
    Inventors: Nikola Nedovic, Sudhir Shrikantha Kudva
  • TECHNIQUES TO IMPROVE CURRENT REGULATOR CAPABILITY TO PROTECT THE SECURED CIRCUIT FROM POWER SIDE CHANNEL ATTACK
    Publication number: 20210336536
    Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
    Type: Application
    Filed: April 23, 2020
    Publication date: October 28, 2021
    Applicant: NVIDIA Corp.
    Inventors: Sudhir Shrikantha Kudva, Nikola Nedovic, Sanquan Song
  • Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O
    Patent number: 11159153
    Abstract: Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: October 26, 2021
    Assignee: NVIDIA Corp.
    Inventors: Donghyuk Lee, James Michael O'Connor, John Wilson
  • Switched low-dropout voltage regulator
    Patent number: 11144080
    Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: October 12, 2021
    Assignee: NVIDIA Corp.
    Inventors: Sudhir Kudva, John Wilson
  • Signal calibration circuit
    Patent number: 11133794
    Abstract: This disclosure relates to a circuit comprising a first, second, and third data latch, and an input for a data signal. The first data latch may be configured to sample a delayed version of the data signal in response to a first control signal. The second data latch may be configured to sample the delayed version of the data signal in response to a run clock signal. The run clock signal may be configured to run for a predefined number of clock cycles subsequent to the first control signal. The third data latch may be configured to sample either an output signal of the first data latch or an output signal of the second data latch in response to a second control signal received after the predefined number of clock cycles of the run clock signal.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: September 28, 2021
    Assignee: NVIDIA Corp.
    Inventors: Stephen G Tell, Matthew Rudolph Fojtik, John Poulton
  • DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
    Publication number: 20210295169
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Application
    Filed: April 15, 2021
    Publication date: September 23, 2021
    Applicant: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Circuit Solution for Managing Power Sequencing
    Publication number: 20210294410
    Abstract: A circuit includes a supply power detector in a first power domain and a ratioed inverter in the first power domain or a second, different power domain. The supply power detector includes an output coupled to an input of the ratioed inverter, and an output of the ratioed inverter provides a power sequencing signal for the second power domain.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 23, 2021
    Applicant: NVIDIA Corp.
    Inventors: Kedar Rajpathak, Tezaswi Raja
  • Reconstruction for temporally dense ray trace rendering
    Patent number: 11120609
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern. Subframes generated based on the sampling order are communicated over a bus along with motion vectors for tiles of the subframes.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: September 14, 2021
    Assignee: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Tomas Guy Akenine-Möller, Jim Nilsson, Marco Salvi, Josef Spjut
  • FAST TRIGGERING ELECTROSTATIC DISCHARGE PROTECTION
    Publication number: 20210281067
    Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Applicant: NVIDIA Corp.
    Inventors: Jauwen Chen, Sunitha Venkataraman, Ting Ku
  • Use of stashing buffers to improve the efficiency of crossbar switches
    Patent number: 11108704
    Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 31, 2021
    Assignee: NVIDIA Corp.
    Inventors: Matthias Augustin Blumrich, Nan Jiang, Larry Robert Dennison
  • ADDRESSING CACHE SLICES IN A LAST LEVEL CACHE
    Publication number: 20210255963
    Abstract: “A system in having M memory controllers between a first memory and a second memory having N operative memory slices, where N and M are not evenly divisible, includes logic to operate the M memory controllers to linearly distribute addresses of the second memory across the N operative memory slices. The system may be utilized in commercial applications such as data centers, autonomous vehicles, and machine learning.
    Type: Application
    Filed: April 13, 2021
    Publication date: August 19, 2021
    Applicant: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang
  • Adaptive pixel sampling order for temporally dense rendering
    Patent number: 11089320
    Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: August 10, 2021
    Assignee: NVIDIA Corp.
    Inventors: Johan Pontus Andersson, Jim Nilsson, Tomas Guy Akenine-Möller
  • Foveated display for augmented reality
    Patent number: 11067806
    Abstract: An augmented reality display system includes a first beam path for a foveal inset image on a holographic optical element, a second beam path for a peripheral display image on the holographic optical element, and pupil position tracking logic that generates control signals to set a position of the foveal inset as perceived through the holographic optical element, to determine the peripheral display image, and to control a moveable stage.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: July 20, 2021
    Assignee: NVIDIA Corp.
    Inventors: Jonghyun Kim, Youngmo Jeong, Michael Stengel, Morgan McGuire, David Luebke
  • AVERAGE POWER ESTIMATION USING GRAPH NEURAL NETWORKS
    Publication number: 20210158155
    Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.
    Type: Application
    Filed: August 13, 2020
    Publication date: May 27, 2021
    Applicant: NVIDIA Corp.
    Inventors: Yanqing Zhang, Haoxing Ren, Brucek Khailany
  • LAYOUT PARASITICS AND DEVICE PARAMETER PREDICTION USING GRAPH NEURAL NETWORKS
    Publication number: 20210158127
    Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.
    Type: Application
    Filed: April 27, 2020
    Publication date: May 27, 2021
    Applicant: NVIDIA Corp.
    Inventors: Haoxing Ren, George Kokai, Ting Ku, Walker Joseph Turner
  • Deep learning based identification of difficult to test nodes
    Patent number: 11010516
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi