Abstract: A system and method for performing sorting. The method includes partitioning a plurality of keys needing sorting into a first plurality of bins, wherein the bins are sequentially sorted. The plurality of keys is capable of being sorted into a sequence of keys using a corresponding ordering system. The method includes coalescing a first pair of consecutive bins, such that when coalesced the first pair of bins falls below a threshold. The method also includes ordering keys in the first coalesced pair to generate a first sub-sequence of keys in the sequence of keys.

Abstract: A method for analyzing race conditions between multiple threads of an application is disclosed. The method comprises accessing hazard records for an application under test. It further comprises creating a graph comprising a plurality of vertices and a plurality of edges using the hazard records, wherein each vertex of the graph comprises information about a code location of a hazard and wherein each edge of the graph comprises hazard information between one or more vertices. Additionally, it comprises assigning each edge with a weight, wherein the weight depends on a number and relative priority of hazards associated with a respective edge. Finally, it comprises traversing the graph to report an analysis record for each hazard represented in the graph.

Abstract: An efficient method and system for estimating an optimal focus position for capturing an image are presented. Embodiments of the present invention initially determine an initial lens position dataset. Then, scores are calculated for each value of the initial lens position dataset producing a plurality of scores. Embodiments of the present invention then determine an optimum focus position through interpolation and extrapolation by relating the initial lens position dataset to the score dataset, in which the score dataset comprises of the plurality of scores.

Abstract: A computer implemented method of simulating a stack of objects represented as data within memory of a computer system is disclosed. The method comprises modeling the stack within a computer simulation as a set of associated primitives with associated constraints thereto in the memory, wherein the stack comprises a plurality of layers and wherein each layer comprises at least one primitive. The method further comprises estimating a height for each of the primitives in the stack and determining a respective scaling factor for each of the primitives in parallel, wherein each scaling factor is operable to adjust a mass value of each of the primitives. Also, the method comprises scaling a mass value of each of the primitives in accordance with a respective scaling factor in parallel. Finally, the method comprises solving over a plurality of constraints iteratively using a scaled mass value for each of the primitives.

Abstract: One embodiment of the present invention sets forth a method for causing thread convergence. The method includes determining that a control flow graph representing a first section of a program includes at least two non-overlapping paths that extend from a first divergent node to a candidate node. The method also includes determining that the first divergent node is not a dominator of the candidate node or that the candidate node is not a post-dominator of the first divergent node. The method further includes identifying an external node and inserting a first instruction configured to cause a predicate variable to be set to true for a first set of threads that is to execute the external node. The method additionally includes inserting into the program a second divergent node configured to cause various threads to execute or not execute a first control flow path associated with the external node.

Abstract: One embodiment of the present invention sets forth a technique for rendering anti-aliased paths by first generating an alpha buffer representing coverage data. To generate the alpha buffer, jittered versions of the rendered path are rendered and corresponding stencil buffers indicating sub-pixel samples of the path that should be covered are generated. After each stencil buffer is generated, the jittered path is rasterized to convert the sub-pixel coverage into coverage weights that are stored in the alpha component of a frame buffer. As each jittered path is rasterized, the coverage weights are accumulated. Finally, geometry representing the union of the jittered versions of the path is rendered to shade pixels based on the accumulated coverage weights. The anti-aliased rendered paths may be filled or stroked without tessellating the paths.

Abstract: A method, an integrated circuit and a system for implementing a secure chain of trust is disclosed. While executing secure boot code in a secure boot mode, less-secure boot code may be authenticated using a secret key. A secure key may also be calculated or generated during the secure boot mode. After control is turned over to the authenticated less-secure boot code, at least one application may be authenticated using the secure key. Once authenticated in the less-secure boot mode, the application may be executed by the programmable integrated circuit. In this manner, a secure chain of trust may be implemented for the programmable integrated circuit.

Abstract: A graphics processing pipeline configured for z-cull operations. The graphics processing pipeline comprising a screen-space pipeline and a tiling unit. The screen-space pipeline includes a z-cull unit configured to perform z-culling operations. The tiling unit is configured to determine that a first set of primitives overlaps a first cache tile. The tiling unit is also configured to transmit the first set of primitives to the screen-space pipeline for processing. The tiling unit is further configured to select between processing the first set of primitives in a full-surface z-cull mode or processing the first set of primitives in a partial-surface z-cull mode. The tiling unit is also configured to cause the z-cull unit to process the first set of primitives in the full-surface z-cull mode or to process the first set of primitives in the partial-surface z-cull mode.

Abstract: A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs.

Abstract: A system, method, and computer program product are provided for implementing a software-based scoreboarding mechanism. The method includes the steps of receiving a dependency barrier instruction that includes an immediate value and an identifier corresponding to a first register and, based on a comparison of the immediate value to the value stored in the first register, dispatching a subsequent instruction to at least a first processing unit of two or more processing units.

Abstract: The server based graphics processing techniques, describer herein, include receiving function calls by a three dimension graphics application programming interface host-guest communication manager (D3D HGCM) service module from one or more given instances of a guest shin layer through a communication channel of a host-guest communication manager (HGCM). The one or more given instances of the guest shim layer are executing under control of a respective given instance of a guest operating system. The HGCM and D3D HGCM service module are executing under control of a host operating system. The rendering context for each function call received from the each instance of the guest shim layer is determined by the D3D HGCM service module. Each function call of a given rendering context is sent by the D3D HGCM service module to a corresponding device specific kernel mode driver of a given graphics processing unit for scheduling execution with the given graphics processing unit of the given rendering context.

Abstract: Systems and devices configured to implement techniques for ensuring the completion of transactions while minimizing latency and power consumption are described. A device may be operably coupled to a bidirectional communications bus. A bidirectional communications bus may include a clock line and a data line. The device may be configured to determine if an initiated transaction corresponds to a device in a low power state. The device may pause the transaction. The device may replay portions of the transaction when the device is in an appropriate power state. The device may replay portions of the transaction using an override interface.

Abstract: A portable electronic device is provided having an audio subsystem with a plurality of audio devices, each of which is coupled to a logic subsystem via its own audio path. The portable electronic device may also include a display configured to present visual content, with the display being fixed in position relative to the plurality of audio devices. The portable electronic device further includes an orientation sensor electronically coupled to the logic subsystem, the logic subsystem being configured, using data received from the orientation sensor, (i) to determine whether the portable electronic device has been reoriented; and (ii) in response to such determination, vary operation of one or more of the audio paths.

Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. Furthermore; the method can include performing packing that includes utilizing varying sized bit fields to produce a compressed representation.

Abstract: A method and apparatus for inserting a watermark into a compiled computer program. A location process specifies an insertion point in the compiled program and a watermark generating process inserts a watermark, based on data to be encoded, into the program at the insertion point. The location process is also utilized to specify the location of watermark data to be decoded.

Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.

Abstract: A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from the multi-issue queue when the parallel processing unit is available. The address divergence unit causes the subset of non-divergent threads to be issued for execution on the parallel processing unit. The address divergence unit repeats the identifying, storing, and causing steps for the remaining threads in the thread group that are not included in the subset of non-divergent threads.

Abstract: Disclosed is a method of providing channel state information for a desired downlink channel of a wireless communication system. In a configuration phase, the method comprises receiving on a signaling channel configuration information comprising an identifier of an interference source and an association which associates the identifier with at least one resource element not used for transmission on the desired downlink channel. In an estimation phase, the method comprises estimating channel state information for an expected transmission on the desired downlink channel accounting for an incoming interference transmission from the identified interference source as observed from the at least one resource element. In a reporting phase, the method comprises reporting the channel state information.

Abstract: A preconditioner processor and a method of computing a preconditioning matrix. In one embodiment, the preconditioner processor has parallel computing pipelines including: (1) a graph coloring circuit operable to identify parallelisms in a sparse linear system, (2) an incomplete lower triangle, upper triangle factorization (ILU) computer configured to employ the parallel computing pipelines according to the parallelisms to: (2a) determine a sparsity pattern for an ILU preconditioning matrix, and (2b) compute non-zero elements of the ILU preconditioning matrix according to the sparsity pattern, and (3) a memory communicably couplable to the parallel computing pipelines and configured to store the ILU preconditioning matrix.

Abstract: For encoding, a frame of video data can be segregated into macroblocks, which can be segregated into slices, which in turn can be segregated into slice groups. A macroblock identifier (ID) can be associated with each of the macroblocks. When at least one slice from each of the slice groups has been encoded, the macroblock IDs associated with the encoded slices can be compared to determine an order in which the encoded slices are to be placed in an access unit for the frame. Of the encoded slices, the slice that includes the macroblock with the lowest macroblock ID will be placed in the access unit before the other encoded slices.