Patents Assigned to NVidia
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Patent number: 9529712Abstract: Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.Type: GrantFiled: July 26, 2011Date of Patent: December 27, 2016Assignee: NVIDIA CORPORATIONInventors: Brian Kelleher, Emmett M. Kilgariff, Wayne Yamamoto
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Patent number: 9530714Abstract: An integrated circuit system includes a heat spreader that is thermally coupled to a semiconductor chip and has a cavity or opening formed in the heat spreader. The cavity or opening is positioned so that capacitors and/or other passive components mounted to the same packaging substrate as the semiconductor chip are at least partially disposed in the cavity or opening. Because the passive components are disposed in the cavity or opening, the integrated circuit system has a reduced package thickness.Type: GrantFiled: December 13, 2012Date of Patent: December 27, 2016Assignee: NVIDIA CorporationInventors: Shantanu Kalchuri, Abraham F. Yee, Leilei Zhang
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Patent number: 9530189Abstract: A method for compressing framebuffer data is presented. The method includes determining a reduction ratio for framebuffer data in a tile including multiple samples. The reduction ratio determined is independent of the sampling mode, where the sampling mode is the number of samples within each pixel in the tile. The method further includes comparing a first portion of the framebuffer data for each of the multiple samples to determine an equality comparison result and also comparing a second portion of the framebuffer data for each one of the multiple samples to compute per-channel differences for each one of the multiple samples and testing the per-channel differences against a threshold value to determine a threshold comparison result. Finally, the method comprises compressing the framebuffer data for the tile based on the reduction ratio, the equality comparison result and the threshold comparison result to produce output framebuffer data for the tile.Type: GrantFiled: December 27, 2012Date of Patent: December 27, 2016Assignee: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, David Kirk McAllister, Steven E. Molnar, Narayan Kulshrestha, Rui Bastos, Joseph Detmer, William Craig McKnight
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Patent number: 9529525Abstract: A method for reducing line display latency on a touchpad device is disclosed. The method comprises storing information regarding a plurality of prior touch events on a touch screen of the touchpad device into an event buffer. It further comprises determining an average speed and a predicted direction of motion of a user interaction with the touch screen using the plurality of prior touch events. Next, it comprises calculating a first prediction point using the average speed, the predicted direction, and a last known touch event on the touch screen. Subsequently, it comprises applying weighted filtering on the first prediction point using a measured line curvature to determine a second prediction point. Finally, it comprises rendering a prediction line between the last known touch event on the touch screen and the second prediction point.Type: GrantFiled: August 30, 2013Date of Patent: December 27, 2016Assignee: NVIDIA CORPORATIONInventors: Bojan Skaljak, Arman Toorians, Michael Chu
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Patent number: 9525401Abstract: Low clocking power flip-flop. In accordance with a first embodiment of the present invention, a flip-flop electronic circuit includes a master latch coupled to a slave latch in a flip-flop configuration. The flip-flop electronic circuit also includes a clock control circuit for comparing an input to the master latch with an output of the slave latch, and responsive to the comparing, blocking a clock signal to the master latch and the slave latch when the flip-flop electronic circuit is in a quiescent condition.Type: GrantFiled: March 11, 2015Date of Patent: December 20, 2016Assignee: NVIDIA CORPORATIONInventors: Xi Zhang, Hwong-Kwo Lin, Ge Yang, Lingfei Deng
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Patent number: 9524138Abstract: In typical embodiments a three GPU configuration is provided comprising three discrete video cards, each connected to a standard monitor placed horizontally for a 3× horizontal resolution. In this configuration, depending on the load on each GPU, the vertical split lines are dynamically adjusted. To adjust the load balancing according to these virtual split lines, the rendering clip rectangle of each GPU is adjusted, in order to reduce the number of pixels rendered by the heavily loaded GPU. These split lines define the boundary of the scene to be rendered by each GPU, and, according to some embodiments, may be moved horizontally. Thus for example if a GPU has a more complex rendering clip polygon to render than the other GPUs, the neighboring GPUs may render the rendering clip polygon it displays plus a portion of the rendering clip polygon to be displayed by heavily loaded GPU.Type: GrantFiled: December 29, 2009Date of Patent: December 20, 2016Assignee: NVIDIA CORPORATIONInventors: Eric Boucher, Franck Diard
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Patent number: 9519144Abstract: A system, method, and computer program product are provided for producing images for a near-eye light field display. Defect information for a first pixel of a microdisplay of a near-eye light field display device is received and a second pixel of the microdisplay is identified, where the first pixel and the second pixel contribute to a portion of the retinal image. Based on the defect information, a value of the second pixel within an array of elemental images is modified to produce a corrected array of elemental images for display by the microdisplay. An optical apparatus of the near-eye light field display device may, for example, be a microlens of a microlens array positioned between a viewer and an emissive microdisplay or a pinlight of a pinlight array positioned behind a transmissive microdisplay relative to the viewer.Type: GrantFiled: July 3, 2014Date of Patent: December 13, 2016Assignee: NVIDIA CorporationInventors: Douglas Robert Lanman, David Patrick Luebke
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Patent number: 9519568Abstract: A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused.Type: GrantFiled: December 31, 2012Date of Patent: December 13, 2016Assignee: NVIDIA CORPORATIONInventors: Mayank Kaushik, Alban Douillet, Geoffrey Gerfin, Vyas Venkataraman, Mark Hairgrove, Riley Andrews
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Patent number: 9519947Abstract: One embodiment of the present invention sets forth a technique for a program to access multi-dimensional formatted graphics surface memory. Multi-dimensional memory objects called “surfaces” stored in a user-specified data or pixel format and arranged in a graphics optimized layout are accessed by programs using surface instructions. A set of memory access instructions e.g., load, store, reduce, and atomic, referred to as surface instructions, may be used to access the surfaces. Coordinate bounds checking is performed with configurable clamping. Caching behavior may also be specified by the surface instructions. Data format conversion and packing to a specified storage format is supported for store, reduction, and atomic surface instructions. Data format conversion and unpacking from a specified storage format is supported for loads and atomic surface instructions.Type: GrantFiled: September 24, 2010Date of Patent: December 13, 2016Assignee: NVIDIA CorporationInventors: John R. Nickolls, Brian Fahs, Lars Nyland, John Erik Lindholm, Richard Craig Johnson
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Patent number: 9516326Abstract: A method for rotating macro-blocks of a frame of a video stream. A degree of rotation for the video stream is accessed. A macro-block of the video stream is accessed. The macro-block is rotated according to the degree of rotation. The macro-block is repositioned to a new position within the frame, wherein the new position is based on the degree of rotation.Type: GrantFiled: December 9, 2005Date of Patent: December 6, 2016Assignee: NVIDIA CorporationInventors: Ignatius B. Tjandrasuwita, Harikrishna M. Reddy, Iole Moccagatta
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Patent number: 9516224Abstract: In one embodiment, a car navigation device is provided. The device comprises: at least one wide-angle camera; a video correction unit for acquiring video data from the wide-angle lens and correcting the video data; a video merging unit for acquiring corrected video data from video correction unit and merging the corrected video data; an image recognition unit for acquiring video from the video merging unit and performing image recognition to the video; and a driving assistant unit for acquiring data from the image recognition unit and assisting driving in accordance with the recognized content. The navigation device provided by various embodiments in accordance with the present invention can correct and recognize the images taken by fisheye lens in real-time so as to assist the driver for driving or drive the car automatically without a human being.Type: GrantFiled: November 14, 2012Date of Patent: December 6, 2016Assignee: NVIDIA CORPORATIONInventor: Wenjie Zheng
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Patent number: 9513975Abstract: One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.Type: GrantFiled: May 2, 2012Date of Patent: December 6, 2016Assignee: NVIDIA CorporationInventors: Stephen Jones, Philip Alexander Cuadra, Daniel Elliot Wexler, Ignacio Llamas, Lacky V. Shah, Jerome F. Duluk, Jr., Christopher Lamb
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Patent number: 9513923Abstract: One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first operator is a PPU context push, which causes a PPU driver to store the current PPU context of a calling thread on a PPU context stack and to associate a named PPU context with the calling thread. The second operator is a PPU context pop, which causes the PPU driver to restore the PPU context of a calling function to the PPU context at the top of the PPU context stack. By performing a PPU context push at the beginning of a function and a PPU context pop prior to returning from the function, the function may execute within a single CPU thread, but operate on a two distinct PPU contexts.Type: GrantFiled: March 30, 2012Date of Patent: December 6, 2016Assignee: NVIDIA CorporationInventor: Nicholas Patrick Wilt
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Patent number: 9510242Abstract: In one embodiment the modem has a network interface, application interface, processor, and memory. The network interface exchanges radio data with a network. The application (or host) interface exchanges application data with an application (or host) processor. The processor converts a unit of radio data to a corresponding unit of application data. The memory stores each unit of application data received by the modem. The processor is configured to execute a selective discard function to reduce traffic by determining if a newly arrived unit of application data is a duplicate of a stored unit of application. In the case that the newly arrived unit of application data is a duplicate of the stored unit of application data, the processor is further configured to selectively discard the duplicate unit of application data in dependence on whether an acknowledgement of the data has been already recognized by the processor.Type: GrantFiled: May 17, 2013Date of Patent: November 29, 2016Assignee: Nvidia CorporationInventors: Flavien Delorme, Fabien Besson, Bruno De Smet
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Patent number: 9508109Abstract: An embodiment of the present invention includes a device for real-time graphics processing. The device includes an interface coupled to exterior for receiving external data. The device includes a data converter coupled to the interface for converting the external data received from the interface. The device includes a graphics processing unit coupled to the data converter to process the external data that has been converted.Type: GrantFiled: January 13, 2012Date of Patent: November 29, 2016Assignee: NVIDIA CORPORATIONInventors: Yanxun Li, Yingliang Jie, Ying Jiao, Xiaobin Yang
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Patent number: 9507470Abstract: Embodiments of the present invention can be configured to recognize and/or track certain types of touch input detected by a touch sensor, such as stylus input, during the performance of standard “full” touch scans in which each drive line of the touch sensor is generally scanned. Upon detection of these input types, “partial” touch scan operations can advantageously be performed which can dynamically reduce the number of lines scanned in a power-saving manner. These partial scans can be configured to intelligently initially scan the area where these input types were last detected so that there is minimal need to return to a previous “full” scan mode. If these specified touch inputs types are not detected during a “partial” scan mode, the touch sensor can be restored to a “full” scan mode until a subsequent detection of the touch input is determined, in which the touch sensor can be returned to a “partial” scan mode. Each time a partial scan is used, power is saved.Type: GrantFiled: December 16, 2013Date of Patent: November 29, 2016Assignee: NVIDIA CorporationInventor: David Jung
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Patent number: 9507378Abstract: An apparatus for dissipating heat is presented. The apparatus comprises a base provided with a recess on a top thereof for containing a portion of a flat panel electronic device. It also comprises a base heat sink disposed in the base. Finally, it comprises a heat-conducting plug with a first end thereof thermally contacting with the base heat sink, and a second end thereof extending upward from a bottom of the recess for plugging into a heat-conducting socket of the flat panel electronic device when the flat panel electronic device is placed on the base.Type: GrantFiled: February 25, 2013Date of Patent: November 29, 2016Assignee: NVIDIA CORPORATIONInventor: Shuang Xu
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Patent number: 9508111Abstract: A method and system for detecting a display mode suitable for a reduced display refresh rate are disclosed. Specifically, one embodiment of the present invention sets forth a computing device, which includes a memory and a processing unit. The memory stores multiple image surface data. The processing unit is configured to compose a first display frame from a first base surface and optionally a first overlay surface, calculate a first numerical code representative of a first frame content of the first display frame, compose a second display frame from a second base surface and optionally a second overlay surface, calculate a second numerical code representative of a second frame content of the second display frame, and track the results of comparing the first numerical code with the second numerical code to determine whether a change between the first frame content and the second frame content has occurred.Type: GrantFiled: December 14, 2007Date of Patent: November 29, 2016Assignee: NVIDIA CorporationInventors: Michael A. Ogrinc, Brett T. Hannigan, David Wyatt
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Patent number: 9509392Abstract: Method, receiver and computer program product for processing a signal transmitted over a wireless network from a plurality of spatially separated transmit antennas of a transmitter using a Multiple-Input Multiple-Output transmission. The signal is received at a plurality of receive antennas, the signal comprising a plurality of data streams. The channel quality for each of the data streams in the received signal is determined and based on the determined channel quality of the data streams, the number of independent data streams that can be supported in the Multiple-Input Multiple-Output transmission of the signal is determined. An indication of the determined number is transmitted to the transmitter.Type: GrantFiled: April 12, 2011Date of Patent: November 29, 2016Assignee: Nvidia Technology UK LimitedInventors: Tarik Tabet, Carlo Luschi
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Patent number: 9508318Abstract: Dynamic white point management techniques include determining a white point of ambient light proximate to a display. A color profile adjustment is determined based upon the determined white point and intensity of the ambient light. The image color space is transformed to a display color space for rendering on the display based on the determined adjusted to the color profile.Type: GrantFiled: December 31, 2012Date of Patent: November 29, 2016Assignee: NVIDIA CORPORATIONInventors: Sean Midthun Pieper, Kurt Roland Wall, Ricardo J. Motta