Abstract: Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.

Abstract: A graphical processing unit having an implementation of a hierarchical hash table thereon, a method of establishing a hierarchical hash table in a graphics processing unit and GPU computing system are disclosed herein. In one embodiment, the graphics processing unit includes: (1) a plurality of parallel processors, wherein each of the plurality of parallel processors includes parallel processing cores, a shared memory coupled to each of the parallel processing cores, and registers, wherein each one of the registers is uniquely associated with one of the parallel processing cores and (2) a controller configured to employ at least one of the registers to establish a hierarchical hash table for a key-value pair of a thread processing on one of the parallel processing cores.

Abstract: One embodiment of the present invention includes a method for performing arithmetic operations on arbitrary width integers using fixed width elements. The method includes receiving a plurality of input operands, segmenting each input operand into multiple sectors, performing a plurality of multiply-add operations based on the multiple sectors to generate a plurality of multiply-add operation results, and combining the multiply-add operation results to generate a final result. One advantage of the disclosed embodiments is that, by using a common fused floating point multiply-add unit to perform arithmetic operations on integers of arbitrary width, the method avoids the area and power penalty of having additional dedicated integer units.

Abstract: Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.

Abstract: Provided is an antenna. The antenna, in this aspect, includes an inverted-F GPS antenna structure, the inverted-F GPS antenna structure embodying a GPS feed element, a GPS extending arm, and a ground element. The antenna, in this aspect, further includes a loop WiFi antenna structure, the loop WiFi antenna structure embodying a WiFi feed element, the ground element, and a WiFi connecting arm coupling the WiFi feed element to the ground element. In this particular aspect, the ground element is located between the GPS feed element and the WiFi feed element.

Abstract: A work distribution unit distributes work batches to general processing clusters (GPCs) based on the number of streaming multiprocessors included in each GPC. Advantageously, each GPC receives an amount of work that is proportional to the amount of processing power afforded by the GPC. Embodiments include a method for distributing batches of processing tasks to two or more general processing clusters (GPCs), including the steps of updating a counter value for each of the two or more GPCs based on the number of enabled parallel processing units within each of the two or more GPCs, and distributing a batch of processing tasks to a first GPC of the two or more GPCs based on a counter value associated with the first GPC and based on a load signal received from the first GPC.

Abstract: A method and a system are provided for controlling memory accesses. Memory access requests including at least a first speculative memory access request and a first non-speculative memory access request are received and a memory access request is selected from the memory access requests. A memory access command is generated to process the selected memory access request.

Abstract: A system, method, and computer program product are provided for implementing a pinlight see-through near-eye display. Light cones configured to substantially fill a field-of-view corresponding to a pupil are generated by an array of pinlights positioned between a near focus plane and the pupil. Overlap regions where two of more light cones intersect at a display layer positioned between the array of pinlights and the pupil are determined. The two or more light cones are modulated based on the overlap regions to produce a target image at or beyond the near focus plane.

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.

Abstract: A subsystem is configured to apply a voltage source to a gated circuit domain in a manner that limits in-rush current and affords minimal time delay. A control signal turns on a wake-up switch that connects the voltage source to the domain. The equivalent series resistance of the wake-up switch has a magnitude that limits the transient charge current to the gated domain. A digital control circuit monitors the resulting rising domain voltage and determines when the domain voltage reaches operating level, at which point additional transient current will be minimal. The control circuit then activates a primary switch that connects the voltage source to the domain through a series resistance of negligible magnitude. An adjustment element provides the option to permanently set a control signal that marginally reduces the time at which the control circuit activates the primary switch to compensate for variations in circuit parameters.

Abstract: A method for simulating visual effects is disclosed. The method comprises modeling each visual effect within a simulation as a set of associated particles with associated constraints applicable thereto. It also comprises predicting first velocities and first positions of a plurality of particles being used to simulate a visual effect based on an external force applied to the plurality of particles. Next, it comprises identifying a set of neighboring particles for each of the plurality of particles. The method also comprises solving a plurality of constraints related to the visual effect, wherein each of the plurality of constraints is solved for the plurality of particles in parallel. Lastly, responsive to the solving, the method comprises determining second velocities and second positions for the plurality of particles.

Abstract: A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. The method can also include performing a prioritized ordering of difference data. Furthermore, the method can include performing packing that includes utilizing varying sized bit fields to produce a lossy compressed representation.

Abstract: One embodiment of the present invention includes a boot read only memory (ROM) with an embedded, private key provision key (KPK) set that enables secure provisioning of chips. As part of taping-out a chip, the chip provider establishes the KPK set and provides the boot ROM exclusive access to the KPK. For each Original Equipment Manufacturer (OEM), the chip provider assigns and discloses an OEM-specific KPK that is included in the KPK set at a particular KPK index. Upon receiving a secured provisioning image and the associated KPK index, the boot ROM accesses the KPK set to reconstruct the KPK and then decrypts and executes the secured provisioning image. Advantageously, this enables the manufacturing factory to provision the chip without the security risks attributable to conventional provisioning approaches that require disclosing security keys to the manufacturing factory.

Abstract: One embodiment of the present invention sets forth a technique for splitting a set of vertices into a plurality of batches for processing. The method includes receiving one or more primitives each containing an associated set of vertices. For each of the one or more primitives, one or more vertices are gathered from the set of vertices, the vertices are arranged into one or more batches, the batch is routed to a processing pipeline line to process each batch as a separate primitive, and the one or more batches are processed to produce results identical to those of processing the entire primitive as a single entity.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: A system, method, and computer program product are provided for producing images for a near-eye light field display. A ray defined by a pixel of a microdisplay and an optical apparatus of a near-eye light field display device is identified and the ray is intersected with a two-dimensional virtual display plane to generate map coordinates corresponding to the pixel. A color for the pixel is computed based on the map coordinates. The optical apparatus of the near-eye light field display device may, for example, be a microlens of a microlens array positioned between a viewer and an emissive microdisplay or a pinlight of a pinlight array positioned behind a transmissive microdisplay relative to the viewer.

Abstract: Various embodiments relating to reducing memory bandwidth consumed by a continuous scan display screen are provided. In one embodiment, an indication of a static image period of a continuous scan display screen is determined. A reference image of a first image format having a first bit depth is converted into a modified image of a second image format having a second bit depth that is less than the first bit depth. During the static image period, the modified image is scanned onto the continuous scan display screen.

Abstract: The description covers a system and method for operating a micro-processing system having a runahead mode of operation. In one implementation, the method includes providing, for a first portion of code, a runahead correlate. When the first portion of code is encountered by the micro-processing system, a determination is made as to whether the system is operating in the runahead mode. If so, the system branches to the runahead correlate, which is specifically configured to identify and resolve latency events likely to occur when the first portion of code is encountered outside of runahead. Branching out of the first portion of code may also be performed based on a determination that a register is poisoned.

Abstract: A method to drive a pixelated display of an electronic device arranged in sight of a user of the device. The method includes receiving a signal that encodes a display image, and controlling the pixelated display based on the signal to form the display image in addition to a latent image, the latent image being configured to illuminate an eye of the user with light of such characteristics as to be unnoticed by the user, but to reveal an orientation of the eye on reflection into a machine-vision system.

Abstract: A system and method for enhanced automatic monoimaging. Embodiments of the present invention are operable for configuring a first camera based on a configuration determination by a second camera. The method includes capturing a first image with the first camera and determining an optical configuration based on an optical measurement performed by a second camera. In one embodiment, the second camera comprises a lower resolution sensor than a sensor of the first camera. The method further includes sending the optical configuration from the second camera to the first camera and adjusting a configuration of the first camera based on the optical configuration. The method further includes capturing a second image with the first camera. The first image and the second image may be preview images.