Patents Assigned to NVidia
  • Patent number: 9578224
    Abstract: A system and method for enhanced automatic monoimaging. Embodiments of the present invention are operable for configuring a first camera based on a configuration determination by a second camera. The method includes capturing a first image with the first camera and determining an optical configuration based on an optical measurement performed by a second camera. In one embodiment, the second camera comprises a lower resolution sensor than a sensor of the first camera. The method further includes sending the optical configuration from the second camera to the first camera and adjusting a configuration of the first camera based on the optical configuration. The method further includes capturing a second image with the first camera. The first image and the second image may be preview images.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 21, 2017
    Assignee: Nvidia Corporation
    Inventors: Guanghua Gary Zhang, Michael Lin, Patrick Shehane, Hugh Phu Nguyen
  • Patent number: 9576340
    Abstract: A technique for efficiently compressing rendered three-dimensional images in a remote rendering system adds a novel render-assisted prediction function to an existing video compression framework, such as the standard H.264/5 framework. Auxiliary rendering information is separated from rendering information used to describe a reference image by a server system. A client system may alter the auxiliary data and generate a new image based on the reference image and rendered scene information from the auxiliary data without creating additional network bandwidth or server workload.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 21, 2017
    Assignee: NVIDIA Corporation
    Inventors: Dawid Stanislaw Pajak, David Luebke, Scott Saulters
  • Patent number: 9575892
    Abstract: One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 21, 2017
    Assignee: NVIDIA Corporation
    Inventors: James Leroy Deming, Jerome F. Duluk, Jr., John Mashey, Mark Hairgrove, Lucien Dunning, Jonathon Stuart Ramsey Evans, Samuel H. Duncan, Cameron Buschardt, Brian Fahs
  • Patent number: 9569279
    Abstract: A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 14, 2017
    Assignee: NVIDIA Corporation
    Inventors: Gary D. Hicok, Matthew Raymond Longnecker, Rahul Gautam Patel
  • Patent number: 9571818
    Abstract: Techniques for generating robust depth maps from stereo images are described. A robust depth map is generated from a set of stereo images captured with and without flash illumination. The depth map is more robust than depth maps generated using conventional techniques because a pixel-matching algorithm is implemented that weights pixels in a matching window according to the ratio of light intensity captured using different flash illumination levels. The ratio map provides a rough estimate of depth relative to neighboring pixels that enables the flash/no-flash pixel-matching algorithm to devalue pixels that appear to be located at different depths than the central pixel in the matching window. In addition, the ratio map may be used to filter the generated depth map to generate a smooth estimate for the depth of objects within the stereo image.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: February 14, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Kari Pulli, Alejandro Troccoli, Changyin Zhou
  • Patent number: 9570907
    Abstract: A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: February 14, 2017
    Assignee: Nvidia Corporation
    Inventors: Gabriele Gorla, Yaoshun Jia, Samuel Duell, Andrew Bell, Qi Lin
  • Patent number: 9569197
    Abstract: Disclosed herein are mobile computing devices that employ compatible updated drivers. In one embodiment, the mobile computing device includes: (1) a processor, (2) a driver library configured to store original drivers and updated drivers for applications on the mobile computing device, and (3) a driver selector configured to determine at least one driver from the original drivers or the updated drivers to use for running one of the applications.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: February 14, 2017
    Assignee: Nvidia Corporation
    Inventors: Nicholas Haemel, Cathy Donovan, Narayanan Swaminathan
  • Patent number: 9569885
    Abstract: One embodiment of the present invention includes techniques for pre-computing ambient shadowing parameters for a computer-generated scene. A processing unit retrieves a reference object associated with the computer-generated scene and comprising a plurality of vertices. For each vertex in the plurality of vertices, the processing unit computes a local ambient shadowing parameter, and stores the local ambient shadowing parameter in a memory. For each instance of the reference object included in the computer-generated scene, the processing unit computes a first global ambient shadowing parameter based on the position of the instance within the computer-generated scene, and stores the first global ambient shadowing parameter in the memory. One advantage of the disclosed embodiments is that ambient obscurance is applied to instance objects in a scene in real time while reducing memory space dedicated to storing the AO parameters.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: February 14, 2017
    Assignee: NVIDIA Corporation
    Inventor: Peter-Pike Johannes Sloan
  • Patent number: 9569348
    Abstract: One embodiment of the present invention sets forth a technique for performing a method for compressing page table entries (PTEs) prior to storing the PTEs in a translation look-aside buffer (TLB). A page table entry (PTE) request is received for a PTE that is not stored in the TLB. The PTE as well as a plurality of PTEs that are adjacent to the PTE are retrieved from a memory. The PTE and the plurality of PTEs are compressed and then stored in the TLB.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: February 14, 2017
    Assignee: NVIDIA Corporation
    Inventors: James Leroy Deming, Mark Allen Mosley, William Craig McKnight
  • Patent number: 9569385
    Abstract: Embodiments are disclosed relating to methods of ordering transactions across a bus of a computing device. One embodiment of a method includes determining a current target memory channel for an incoming transaction request, and passing the incoming transaction request downstream if the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter or the counter equals zero. The method further includes holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 14, 2017
    Assignee: Nvidia Corporation
    Inventors: Sagheer Ahmad, Dick Reohr
  • Patent number: 9570284
    Abstract: A method for controlling a semiconductor fabrication process includes the steps of analyzing process-data related to an intermediate-process-step in the fabrication process and adjusting a metal-layer-parameter corresponding to the metal layer based on the process-data.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: February 14, 2017
    Assignee: NVIDIA Corporation
    Inventor: Abraham F. Yee
  • Patent number: 9569559
    Abstract: An apparatus, computer readable medium, and method are disclosed for performing an intersection query between a query beam and a target bounding volume. The target bounding volume may comprise an axis-aligned bounding box (AABB) associated with a bounding volume hierarchy (BVH) tree. An intersection query comprising beam information associated with the query beam and slab boundary information for a first dimension of a target bounding volume is received. Intersection parameter values are calculated for the first dimension based on the beam information and the slab boundary information and a slab intersection case is determined for the first dimension based on the beam information. A parametric variable range for the first dimension is assigned based on the slab intersection case and the intersection parameter values and it is determined whether the query beam intersects the target bounding volume based on at least the parametric variable range for the first dimension.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: February 14, 2017
    Assignee: NVIDIA Corporation
    Inventors: Tero Tapani Karras, Timo Oskari Aila, Samuli Matias Laine, John Erik Lindholm
  • Patent number: 9569214
    Abstract: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: February 14, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Gokul Govindu, Parag Gupta, Scott Pitkethly, Guillermo J. Rozas
  • Patent number: 9563562
    Abstract: Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: February 7, 2017
    Assignee: Nvidia Corporation
    Inventors: Joseph Rowlands, Anurag Chaudhary
  • Patent number: 9563227
    Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 7, 2017
    Assignee: NVIDIA CORPORATION
    Inventor: Tom J. Verbeure
  • Patent number: 9563432
    Abstract: Various embodiments relating to executing different types of instruction code in a micro-processing system are provided.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: February 7, 2017
    Assignee: Nvidia Corporation
    Inventors: Ross Segelken, Darrell D. Boggs, Shiaoli Mendyke
  • Patent number: 9563933
    Abstract: Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 7, 2017
    Assignee: Nvidia Corporation
    Inventors: Vinod Grover, Mahesh Ravishankar
  • Patent number: 9557565
    Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels. The apparatus may further include a computer system coupled with the display and operable to instruct the display to display a deconvolved image corresponding to a target image, wherein when the display displays the deconvolved image while located within a near-eye range of an observer, the target image may be perceived in focus by the observer.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: January 31, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: David Patrick Luebke, Douglas Lanman, Thomas F. Fox, Gerrit Slavenburg
  • Patent number: 9558573
    Abstract: A technique for efficiently rendering path images tessellates path contours into triangle tans comprising a set of representative triangles. Topology of the set of representative triangles is then optimized for greater rasterization efficiency by applying a flip operator to selected triangle pairs within the set of representative triangles. The optimized triangle pairs are then rendered using a path rendering technique, such as stencil and cover.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: January 31, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard
  • Patent number: 9558712
    Abstract: A computer implemented method of determining a latent image from an observed image is disclosed. The method comprises implementing a plurality of image processing operations within a single optimization framework, wherein the single optimization framework comprises solving a linear minimization expression. The method further comprises mapping the linear minimization expression onto at least one non-linear solver. Further, the method comprises using the non-linear solver, iteratively solving the linear minimization expression in order to extract the latent image from the observed image, wherein the linear minimization expression comprises: a data term, and a regularization term, and wherein the regularization term comprises a plurality of non-linear image priors.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: January 31, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Dawid Stanislaw Pajak, Felix Heide, Nagilla Dikpal Reddy, Mushfiqur Rouf, Jan Kautz, Kari Pulli, Orazio Gallo