Abstract: A technique is disclosed for executing a compiled parallel application on a general purpose processor. The compiled parallel application comprises parallel thread execution code, which includes single-instruction multiple-data (SIMD) constructs, as well as references to intrinsic functions conventionally available in a graphics processing unit. The parallel thread execution code is transformed into an intermediate representation, which includes vector instruction constructs. The SIMD constructs are mapped to vector instructions available within the intermediate representation. Intrinsic functions are mapped to corresponding emulated runtime implementations. The technique advantageously enables parallel applications compiled for execution on a graphics processing unit to be executed on a general purpose central processing unit configured to support vector instructions.

Abstract: A modem and a method for handing over Internet protocol (IP) multimedia subsystem (IMS) sessions from a packet-switched network to a circuit-switched network. One embodiment of the modem includes: (1) a physical layer through which IMS packets for a plurality of IMS sessions are transmittable and receivable, and (2) a control layer configured to gain access to respective IMS session data for the plurality of IMS sessions, the respective IMS session data originating from a host IMS application.

Abstract: A parallel counter accesses data generated by an application and stored within a register. The register includes different segments that include different portions of the application data. The parallel counter is configured to count the number of values within each segment that have a particular characteristic in a parallel fashion. The parallel counter may then return the individual segment counts to the application, or combine those segment counts and return a register count to the application. Advantageously, applications that rely on population count operations may be accelerated. Further, increasing the number of segments in a given register may reduce the time needed to count the values in that register, thereby providing a scalable solution to population counting. Additionally, the architecture of the parallel counter is sufficiently flexible to allow both register counting and segment counting, thereby combining two separate functionalities into just one hardware unit.

Abstract: A jitter buffering system and a method of jitter buffering. The jitter buffering system may be embodied in a quality of service (QoS) management server, including: (1) a network interface controller (NIC) configured to receive one-way-delay statistics regarding a video stream transmitted to a client, and (2) a processer configured to employ the one-way-delay statistics to calculate and recognize jitter and subsequently generate a command for the client to enable jitter buffering.

Abstract: A packaged memory device includes a semiconductor interposer, a first memory stack, a second memory stack, and a buffer chip that are all coupled to the semiconductor interposer. The first memory stack and the second memory stack each include multiple memory chips that are configured as a single stack. The buffer chip is electrically coupled to the first memory stack via a first data bus, electrically coupled to the second memory stack via a second data bus, and electrically coupled to a processor data bus that is configured for transmitting signals between the buffer chip and a processor chip. Such a memory device can have high data capacity and still operate at a high data transfer rate in an energy efficient manner.

Abstract: A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.

Abstract: A method of processing digital video signals, comprising: receiving input pixels to be processed; performing multiple processing operations on the input pixels, where the multiple processing operations are performed during a time interval determined in part by a desired video output rate; and performing a classification analysis at an intermediate time during the time interval, the classification analysis yielding tag data that is used to dynamically vary one or more of the multiple processing operations, and where the tag data is generated on a per-pixel basis to enable pixel by pixel variation of the multiple processing operations.

Abstract: A system, method, and computer program product are provided for shading primitive fragments. A target buffer may be recast when shaded samples that are covered by a primitive fragment are generated at a first shading rate using a first sampling mode, the shaded samples are stored in the target buffer that is associated with the first sampling mode and the first shading rate, a second sampling mode is determined, and the target buffer is associated with the second sampling mode. A sampling mode and/or shading rate may be changed for a primitive. A primitive fragment that is associated with a first sampling mode and a first shading rate is received and a second sampling mode is determined for the primitive fragment. Shaded samples corresponding to the primitive fragment are generated, at a second shading rate, using the second sampling mode and the shaded samples are stored in a target buffer.

Abstract: One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.

Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.

Abstract: A system and method are provided for performing joint color and depth encoding. Color data and depth data for an image is received. Based on the color data, confidence values are computed for the depth data and the depth data is encoded based on the confidence values to represent a correlated portion of the depth data and a decorrelated portion of the depth data. In one embodiment, the depth data comprises per-pixel vergence angles.

Abstract: A system, method, and computer program product are provided for utilizing a wavefront path tracer. In use, a set of light transport paths associated with a scene is identified. Additionally, parallel path tracing is performed, utilizing a wavefront path tracer.

Abstract: A tag unit configured to manage a cache unit includes a coalescer that implements a set hashing function. The set hashing function maps a virtual address to a particular content-addressable memory unit (CAM). The coalescer implements the set hashing function by splitting the virtual address into upper, middle, and lower portions. The upper portion is further divided into even-indexed bits and odd-indexed bits. The even-indexed bits are reduced to a single bit using a XOR tree, and the odd-indexed are reduced in like fashion. Those single bits are combined with the middle portion of the virtual address to provide a CAM number that identifies a particular CAM. The identified CAM is queried to determine the presence of a tag portion of the virtual address, indicating a cache hit or cache miss.

Abstract: One embodiment of the present invention sets for a method for accessing data objects stored in a memory that is accessible by a graphics processing unit (GPU). The method comprises the steps of creating a data object in the memory based on a command received from an application program, wherein the data object is organized non-linearly in the memory, transmitting a first handle associated with the data object to the application program such that data associated with different draw commands can be accessed by the GPU, wherein the first handle includes an address related to the location of the data object in the memory, receiving a first draw command as well as the first handle from the application program, and transmitting the first draw command and the first handle to the GPU for processing.

Abstract: One embodiment of the present invention sets forth a technique for computing dynamic random access memory (DRAM) addresses from linear physical addresses for memory subsystems implementing integral power of two virtual page sizes, and an arbitrary number of available partitions. Each DRAM address comprises a row address, column address, bank address, and partition address. The linear physical address is used to generate to the DRAM address in units of a DRAM bank size. Address scrambling may be implemented to overcome transient access contention to specific DRAM pages by multiple client modules.

Abstract: A touch-screen input/output device including a touch sensor, a display, a display control module, a touch sensor control module and a synchronizer module. The touch sensor is overlaid on a display. The display control module is communicatively coupled to the display and converts video data into a serial bit stream video display signal including one or more blanking intervals. The touch sensor control module is communicatively coupled to the touch sensor and determines touch events and location of the touch event on the touch sensor during one or more touch sensor scan cycles. The synchronizer module is communicatively coupled between the display control module and the touch sensor control module, and interleaves the one or more touch sensor scan cycles with the one or more blanking intervals of the video display signal.

Abstract: Embodiments of the invention provide an integrated circuit system, which includes a first supporting substrate and a second supporting substrate, a logic chip disposed between the first supporting substrate and the second supporting substrate, and a plurality of memory stacks disposed adjacent to one another on a surface of the logic chip. The logic chip is separated from the first supporting substrate and the second supporting substrate by a distance such that at least a portion of a first memory stack in the plurality of memory stacks extending outwards past a first side edge of the logic chip is supported by the first supporting substrate, and at least a portion of a second memory stack in the plurality of memory stacks extending outwards past a second side edge of the logic chip that is opposite to the first side edge is supported by the second supporting substrate.

Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.

Abstract: One embodiment sets forth a method for modifying draw calls using a draw-call shader program included in a processing subsystem configured to process draw calls. The draw call shader receives a draw call from a software application, evaluates graphics state information included in the draw call, generates modified graphics state information, and generates a modified draw call that includes the modified graphics state information. Subsequently, the draw-call shader causes the modified draw call to be executed within a graphics processing pipeline. By performing the computations associated with generating the modified draw call on-the-fly within the processing subsystem, the draw-call shader decreases the amount of system memory required to render graphics while increasing the overall processing efficiency of the graphics processing pipeline.

Abstract: One embodiment of the present invention includes a method for generating accumulated bounding boxes for graphics primitives. The method includes generating a first bounding box associated with a first graphics primitive. The method further includes, for each graphics primitive included in a first set of one or more additional graphics primitives, determining that the graphics primitive is within a threshold distance of the first bounding box, and adding the graphics primitive to the first bounding box. The method further includes determining not to add a second graphics primitive to the first bounding box. The method further includes generating a second bounding box associated with the second graphics primitive. Finally, the method includes transmitting the first bounding box to a tiling unit via a crossbar. One advantage of the disclosed embodiments is that multiple bounding boxes are combined to generate an accumulated bounding box that is then transferred across the crossbar.