Abstract: A memory device and a system that implements a single symbol correction, double symbol detection (SSC-DSD+) error correction scheme are provided. The scheme is implemented by calculating four syndrome symbols in accordance with a Reed-Solomon (RS) codeword; determining three location bytes in accordance with three corresponding pairs of syndrome symbols in the four syndrome symbols; and generating an output based on a comparison of the three location bytes. The output may include: corrected data responsive to determining that the three location bytes match; an indication of a detected-and-corrected error (DCE) responsive to determining that two of the three location bytes match; or an indication of a detected-yet-uncorrected error (DUE) responsive to determining that none of the three location bytes match. A variant of the SSC-DSD+ decoder may be implemented using a carry-free subtraction operation to perform sanity checking.

Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a number of multi-dimensional column-based heat dissipation features enable cooling by a cooling media flowing there through so that an individual heat dissipation column having a first dimension and a second dimension may be supported, with the first dimension being normal relative to an axial flow path of the cooling media, with the second dimension being parallel or offset from parallel relative to the axial flow path and with the second dimension being more than the first dimension.

Abstract: In various examples, a 3D surface structure such as the 3D surface structure of a road (3D road surface) may be observed and estimated to generate a 3D point cloud or other representation of the 3D surface structure. Since the representation may be sparse, one or more densification techniques may be applied to densify the representation of the 3D surface structure. For example, the relationship between sparse and dense projection images (e.g., 2D height maps) may be modeled with a Markov random field, and Maximum a Posterior (MAP) inference may be performed using a corresponding joint probability distribution to estimate the most likely dense values given the sparse values. The resulting dense representation of the 3D surface structure may be provided to an autonomous vehicle drive stack to enable safe and comfortable planning and control of the autonomous vehicle.

Abstract: In various examples, machine learning of encoding parameter values for a network is performed using a video encoder. Feedback associated with streaming video encoded by a video encoder over a network may be applied to an MLM(s). Using such feedback, the MLM(s) may predict a value(s) of an encoding parameter(s). The video encoder may then use the value to encode subsequent video data for the streaming. By using the video encoder in training, the MLM(s) may learn based on actual encoded parameter values of the video encoder. The MLM(s) may be trained via reinforcement learning based on video encoded by the video encoder. A rewards metric(s) may be used to train the MLM(s) using data generated or applied to the physical network in which the MLM(s) is to be deployed and/or a simulation thereof. Penalty metric(s) (e.g., the quantity of dropped frames) may also be used to train the MLM(s).

Abstract: Storage processing units or SPUs (120) operate backend storage (150) to provide scalable storage services, redundancy, and disaster recovery to an enterprise. Each SPU (120) may reside in a host server (110) and may include an processor domain (490) with backup power (440) and isolation from a host domain (480) to allow the SPU (120) to operate after the host (110) fails or otherwise stops providing power. A cloud-based management system (180) may assess the storage needs of the enterprise, identify a storage style suited to the enterprise, and direct the SPUs (120) to create virtual volumes (122, 124, 128) having characteristics according to the storage style identified. The cloud based management system (180) may eliminate the need for the enterprise to have expertise in storage management.

Abstract: A process for manufacturing inductors for use in integrated circuits includes embedding ferromagnetic material in a bulk silicon substrate, forming a plurality of vias in the bulk silicon substrate such that the vias bracket a volume of the bulk silicon substrate that includes the ferromagnetic material, slicing the bulk silicon substrate to form a silicon wafer, and configuring traces between top metal pads of the vias and between bottom metal pads of the vias to form a continuous path for current to flow circumferentially from a first end of the volume to a second end of the volume.

Abstract: Embodiments of the present disclosure relate to memory page access instrumentation for generating a memory access profile. The memory access profile may be used to co-locate data near the processing unit that accesses the data, reducing memory access energy by minimizing distances to access data that is co-located with a different processing unit (i.e., remote data). Execution thread arrays and memory pages for execution of a program are partitioned across multiple processing units. The partitions are then each mapped to a specific processing unit to minimize inter-partition traffic given the processing unit physical topology.

Abstract: One embodiment sets forth a technique for performing one or more matrix multiplication operations based on a first matrix and a second matrix. The technique includes receiving data associated with the first matrix from a first traversal engine that accesses nonzero elements included in the first matrix via a first tree structure. The technique also includes performing one or more computations on the data associated with the first matrix and the data associated with the second matrix to produce a plurality of partial results. The technique further includes combining the plurality of partial results into one or more intermediate results and storing the one or more intermediate results in a first buffer memory.

Abstract: Apparatuses, systems, and techniques to grasp objects with a robot. In at least one embodiment, a neural network is trained to determine a grasp pose of an object within a cluttered scene using a point cloud generated by a depth camera.

Abstract: Various techniques for accelerating dynamic programming algorithms are provided. For example, a fused addition and comparison instruction, a three-operand comparison instruction, and a two-operand comparison instruction are used to accelerate a Needleman-Wunsch algorithm that determines an optimized global alignment of subsequences over two entire sequences. In another example, the fused addition and comparison instruction is used in an innermost loop of a Floyd-Warshall algorithm to reduce the number of instructions required to determine shortest paths between pairs of vertices in a graph. In another example, a two-way single instruction multiple data (SIMD) floating point variant of the three-operand comparison instruction is used to reduce the number of instructions required to determine the median of an array of floating point values.

Abstract: Various embodiments include a memory device that is capable of performing memory access operations with reduced power consumption relative to prior approaches. The memory device receives early indication as to whether a forthcoming memory access operation is a read operation or a write operation. The memory device enables various circuits and disables other circuits depending on whether this early indication identifies an upcoming memory access operation as a read operation or a write operation. As a result, circuits that are not needed for an upcoming memory access operation are disabled earlier during the memory access operation relative to prior approaches. Disabling such circuits earlier during the memory access operation reduces power consumption without reducing memory device performance.

Abstract: Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components using an asynchronous accumulator to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum.

Abstract: Systems and methods are disclosed for fused processing of a continuous mathematical operator. Fused processing of continuous mathematical operations, such as pointwise non-linear functions without storing intermediate results to memory improves performance when the memory bus bandwidth is limited. In an embodiment, a continuous mathematical operation including at least two of convolution, upsampling, pointwise non-linear function, and downsampling is executed to process input data and generate alias-free output data. In an embodiment, the input data is spatially tiled for processing in parallel such that the intermediate results generated during processing of the input data for each tile may be stored in a shared memory within the processor. Storing the intermediate data in the shared memory improves performance compared with storing the intermediate data to the external memory and loading the intermediate data from the external memory.

Abstract: Various types of image analysis benefit from a multi-stream architecture that allows the analysis to consider shape data. A shape stream can process image data in parallel with a primary stream, where data from layers of a network in the primary stream is provided as input to a network of the shape stream. The shape data can be fused with the primary analysis data to produce more accurate output, such as to produce accurate boundary information when the shape data is used with semantic segmentation data produced by the primary stream. A gate structure can be used to connect the intermediate layers of the primary and shape streams, using higher level activations to gate lower level activations in the shape stream. Such a gate structure can help focus the shape stream on the relevant information and reduces any additional weight of the shape stream.

Abstract: Apparatuses, systems, and techniques to generate a trusted execution environment including multiple accelerators. In at least one embodiment, a parallel processing unit (PPU), such as a graphics processing unit (GPU), operates in a secure execution mode including a protect memory region. Furthermore, in an embodiment, a cryptographic key is utilized to protect data during transmission between the accelerators.

Abstract: A cooling system for a datacenter device is disclosed. Fins are provided between a first plate and a second plate to dissipate a first amount of heat to an environment in a first configuration of the fins. The first plate is movable relative to the second plate to expose a surface area of the fins to the environment in a second configuration of the fins.

Abstract: Systems and methods for generating a representative value of a data set by first compressing a portion of values in the data set to determine a first common value and further compressing a subset of the portion of values to determine a second common value. The representative value is generated by taking the difference between the first common value and the second common value, wherein the representative value corresponds to a mathematical relationship between the first and second common values and each value within the subset of the portion of values. The representative value requires less storage than the first and second common values.

Abstract: A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and/or an external memory.

Abstract: Devices and methods for physical chip security are disclosed. In at least one embodiment, a security module is secured to a board to restrict physical access to an integrated circuit mounted on the security module and provides one or more contacts enabling data access to the integrated circuit.

Abstract: Systems and methods are disclosed that improve output quality of any neural network, particularly an image generative neural network. In the real world, details of different scale tend to transform hierarchically. For example, moving a person's head causes the nose to move, which in turn moves the skin pores on the nose. Conventional generative neural networks do not synthesize images in a natural hierarchical manner: the coarse features seem to mainly control the presence of finer features, but not the precise positions of the finer features. Instead, much of the fine detail appears to be fixed to pixel coordinates which is a manifestation of aliasing. Aliasing breaks the illusion of a solid and coherent object moving in space. A generative neural network with reduced aliasing provides an architecture that exhibits a more natural transformation hierarchy, where the exact sub-pixel position of each feature is inherited from underlying coarse features.