Abstract: A system and method for solving linear complementarity problems for rigid body simulation is disclosed. The method includes determining one or more contact constraints affecting an original object having an original mass. The method includes splitting the original object by a total number of the contact constraints into a plurality of sub-bodies. The method includes assigning a contact constraint to a corresponding sub-body. The method further includes solving contact constraints in isolation for each sub-body. The method also includes enforcing fixed joint constraints exactly, such that positions and orientations of each sub-body are identical.

Abstract: A system, method, and computer program product for generating executable code for performing large integer operations on a parallel processing unit is disclosed. The method includes the steps of compiling a source code linked to a large integer library to generate an executable file and executing the executable file to perform a large integer operation using a parallel processing unit. The large integer library includes functions for processing large integers that are optimized for the parallel processing unit.

Abstract: A system, method, and computer program product for testing and classifying silicon wafers using a support vector machine. The method includes the steps of receiving parametric data associated with one or more die on a wafer and analyzing the parametric data via a support vector machine to determine a classification for each die of the one or more die. The parametric data includes at least one ring oscillator ratio. The method further includes the step of determining a classification of the wafer based on the classification of the one or more die.

Abstract: A processor and a system are provided for performing texturing operations. The processor includes a texture return buffer having a plurality of slots for storing texture values and one or more texture units coupled to the texture return buffer. Each of the slots of the texture return buffer are addressable by a thread. Each texture unit is configured to allocate a slot of the texture return buffer when the texture unit generates a texture value.

Abstract: A method includes abstracting, through a driver component, a Graphics Processing Unit (GPU) of a data processing device as a set of GPUs. The GPU is configured to be received in an expansion port on a motherboard of the data processing device. The method also includes enabling, through the abstraction, utilization of a more number of lanes on the expansion port and/or another expansion port on the motherboard of the data processing device than a capability of the GPU otherwise.

Abstract: A system and method for solving linear complementarity problems for rigid body simulation is disclosed. The method includes determining a plurality of modified effective masses for a plurality of contacts between a plurality of bodies, wherein each modified effective mass term is based on a corresponding number of contacts. A plurality of relative velocities is determined based on the plurality of body velocities determined from a last iteration. A plurality of impulse corrections is determined based on the plurality of modified effective masses and the plurality of relative velocities. A plurality of updated impulses is determined based on the impulse corrections. The plurality of updated impulses is applied to the plurality of bodies based on a plurality of original masses of the bodies, body velocities determined from the last iteration, to determine a plurality of updated velocities of the plurality of bodies.

Abstract: A processor and a system are provided for performing texturing operations loaded from a texture queue that provides temporary storage of texture coordinates and texture values. The processor includes a texture queue implemented in a memory of the processor, a crossbar coupled to the texture queue, and one or more texture units coupled to the texture queue via the crossbar. The crossbar is configured to reorder texture coordinates for consumption by the one or more texture units and to reorder texture values received from the one or more texture units.

Abstract: A system, method, and computer program product are provided for a display multiplier. First image data is received for a first display device and second image data is received for a second display device, where the second display device has fewer scan lines than the first display device. A scan line of the second image data is duplicated and a display multiplier output stream is generated that includes a first scan line of the first image data, the scan line of the second image data, a second scan line of the first image data, and the duplicated scan line of the second image data.

Abstract: A method of envelope tracking and an envelope tracking (ET) circuit. One embodiment of the (ET) circuit is for radio frequency (RF) transmission and includes: (1) an amplitude calculator configured to generate an amplitude signal that approximates the amplitude of an input signal, (2) a peak detector configured to take samples of the amplitude signal within a time window and produce an envelope signal that represents an amplitude peak among the samples, and (3) a signal conditioner configured to condition the envelope signal for driving a power supply input stage of a power amplifier operable to amplify and transmit an RF signal based on the input signal.

Abstract: A cooling subsystem is provided for dissipating heat from processor. The cooling subsystem includes a heat sink comprising an upper portion having a plurality of fins formed therein and a base portion fixed to the upper portion to form a vapor chamber in an enclosed volume between the upper portion and the base portion.

Abstract: A First-in First-out (FIFO) memory comprising a latch array and a RAM array and operable to buffer data for multiple threads. Each array is partitioned into multiple sections, and each array comprises a section designated to buffer data for a respective thread. A respective latch array section is assigned higher priority to receive data for a respective thread than the corresponding RAM array section. Incoming data for the respective thread are pushed into the corresponding latch array section while it has vacancies. Upon the latch array section becoming empty, incoming data are pushed into the corresponding RAM array section during a spill-over period. The RAM array section may comprise two spill regions with only one active to receive data at a spill-over period. The allocation of data among the latch array and the spill regions of the RAM array can be transparent to external logic.

Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

Abstract: A double-edge-triggered flip-flop circuit and a method for operating the double-edge-trigger flip-flop circuit are provided. Sub-circuits of a flip-flop circuit are coupled to a ground supply and decoupled the sub-circuits from a power supply when a clock signal is asserted. The sub-circuits generate trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated, levels of the second pair of signals are maintained when the clock signal is asserted, and an output signal is transitioned to equal an input signal based on the trigger signals when the clock signal is asserted.

Abstract: A technique for performing stream output operations in a parallel processing system is disclosed. A stream synchronization unit is provided that enables the parallel processing unit to track batches of vertices being processed in a graphics processing pipeline. A plurality of stream output units is also provided, where each stream output unit writes vertex attribute data to one or more stream output buffers for a portion of the batches of vertices. A messaging protocol is implemented between the stream synchronization unit and the plurality of stream output units that ensures that each of the stream output units writes vertex attribute data for the particular batch of vertices distributed to that particular stream output unit in the same order in the stream output buffers as the order in which the batch of vertices was received from a device driver by the parallel processing unit.

Abstract: Circuits, methods, and apparatus that perform a context switch quickly while not wasting a significant amount of in-progress work. A texture pipeline includes a cutoff point or stage. After receipt of a context switch instruction, texture requests and state updates above the cutoff point are stored in a memory, while those below the cutoff point are processed before the context switch is completed. After this processing is complete, global states in the texture pipeline are stored in the memory. A previous context may then be restored by reading its texture requests and global states from the memory and loading them into the texture pipeline. The location of the cutoff point can be a point in the pipeline where a texture request can no longer result in a page fault in the memory.

Abstract: A method of sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device. The method comprises: determining whether at least one of the data signal and the clock signal is disturbing in that it has a harmonic within the radio frequency band. If it is determined that at least one of the data signal and the clock signal is disturbing, the method further comprises: scrambling the at least one disturbing signal to flatten the spectrum thereof for frequencies below the clock frequency FC, setting a respective at least one indicator to indicate that the at least one disturbing signal has been scrambled, and sending the at least one scrambled signal between the radio frequency circuit and the baseband circuit. The method further comprises, subsequent to the step of sending the at least one scrambled signal, descrambling the at least one scrambled signal if the respective at least one indicator is set.

Abstract: A system and method are provided for sensing current. A current source is configured to generate a current and a pulsed sense enable signal is generated. A sense voltage across a resistive sense mechanism is sampled according to the sense enable signal, where the sense voltage represents a measurement of the current. A system includes the current source and a current sensing unit. The current source is configured to generate a current. The current sensing unit is coupled the current source and is configured to generate a pulsed sense enable signal and sample the sense voltage across a resistive sense mechanism according to the pulsed sense enable signal.

Abstract: A modem for handling notifications received over a network is disclosed. In one embodiment, the modem includes a first interface to connect to a network, a second interface to connect to a host processor on a terminal and a modem processor to receive presence configuration information from the host processor and in response thereto transmit a request comprising the presence configuration information to a presence information store. The modem processor further arranged to receive one or more notifications with presence information from the store based on the presence configuration information in the request. The presence information supplied to the store by one or more further terminals associated with one or more users. The modem processor stores the one or more notifications in a storage means, and in response to receiving a request for presence information from said host processor, supply presence information thereto based on the one or more notifications.

Abstract: A first transceiver is configured to transmit a first data signal to a second transceiver across a communication link. The second transceiver maintains clock data recovery (CDR) lock with the first signal by adjusting a sampling clock configured to sample the first data signal. When the communication link reverses directions, the second transceiver is configured to transmit a second data signal to the first transceiver with the phase of that second data signal adjusted based on the adjustments made to the sampling clock.

Abstract: Attributes of graphics objects are processed in a plurality of graphics processing pipelines. A streaming multiprocessor (SM) retrieves a first set of parameters associated with a set of graphics objects from a first set of buffers. The SM performs a first set of operations on the first set of parameters according to a first phase of processing to produce a second set of parameters stored in a second set of buffers. The SM performs a second set of operations on the second set of parameters according to a second phase of processing to produce a third set of parameters stored in a third set of buffers. One advantage of the disclosed techniques is that work is redistributed from a first phase to a second phase of graphics processing without having to copy the attributes to and retrieve the attributes from the cache or system memory, resulting in reduced power consumption.