Abstract: An administrator system provided according to an aspect of the present invention enables the configuration of display properties of display units on remote systems to desired values. In an embodiment, the user can specify the desired values for multiple systems together. The remote systems may further enable the previously configured values of the display properties to be displayed on the administrator system.

Abstract: A video processor is described, which is useful for implementing a forward transform process, in compliance with the H.264 standard. The video processor includes an input, for receiving a block of image data. The image data is loaded into an internal register. In response to receiving a SIMD instruction, a multiplier, which incorporates the H.264 forward transform matrix in its associated hardware, processes the block of image data, and writes the resulting partially transformed pixel data back to the internal register, transposing the data during the process.

Abstract: Systems and methods for communicating private information from a browser to a driver are presented. The private information communication method can comprise: performing a private information communication process in which private information is communicated through a private information communication plug-in of a browser to a driver; and performing a driver process based upon the private communication information communicated in the private information communication process. The private information communication process can comprise determining private information content; communicating the private information to the private information communication plug-in coupled to a private communication channel; calling a graphics driver from the private information communication plug-in using the private communication channel; and forwarding the private information from the private information communication plug to the driver via the private communication channel.

Abstract: An encoder provided according to an aspect of the present invention uses an approach which seeks to limit the number of bits in each of a sequence of video frames to a same upper limit. By providing such a restriction, additional budget (i.e., more number of bits that can be used for the encoded bits for the frame) may be available for encoding of later received frames in the sequence, thereby avoiding quality degradation with respect to reproduction of such later frames. According to another aspect of the present invention, a quantization parameter used during encoding is controlled to enforce such a limit. According to one more aspect of the present invention, a quantization parameter is generated for a video frame by examining content corresponding to the same video frame.

Abstract: A system and method are provided for regulating a voltage level at a load. A current source generates a current and a voltage control mechanism provides a portion of the current to regulate the voltage level at the load. When the voltage level at the load is greater than a maximum voltage level, the current source is decoupled from the load and the current source is coupled to a current sink to reduce the voltage level at the load. An electric power conversion comprises the current source and the voltage control mechanism. A downstream controller is configured to control the voltage control mechanism to decouple the current source from the load and couple the current source to a current sink to reduce the voltage level at the load when the voltage level at the load is greater than a maximum voltage level.

Abstract: A system, method, and computer program product are provided for verifying sensitivity test program stability. A sensitivity test program including a set of tests is run on a plurality of integrated circuit die fabricated on a silicon wafer, where each test in the set of tests specifies a different set of operating parameters for structures within each integrated circuit die. Results of the sensitivity test program are received for each integrated circuit die and the results of the sensitivity test program are stored in shadow bins allocated within a memory, where each shadow bin corresponds to a different test in the set of tests. The results may be used to verify and optimize operating voltage and operating frequency of different tests in the production test program and wafer fabrication process sensitivity.

Abstract: Computer system, method and computer program product for scheduling IPC activities are disclosed. In one embodiment, the computer system includes first processor and second processors that communicate with each other via IPC activities. The second processor may operate in a first mode in which the second processor is able to process IPC activities, or a second mode in which the second processor does not process IPC activities. Processing apparatus associated with the first processor identifies which of the pending IPC activities for communicating from the first processor to the second processor are not real-time sensitive, and schedules the identified IPC activities for communicating from the first processor to the second processor by delaying some of the identified IPC activities to thereby group them together. The grouped IPC activities are scheduled for communicating to the second processor during a period in which the second processor is continuously in the first mode.

Abstract: A modem is disclosed, one embodiment including: first and second interface apparatuses; and a processing apparatus arranged to transmit a request message to part of a wireless cellular network to request establishment of a channel to access a packet-based network, wherein the request message requests the channel as being of a type that supports both a first and second version of a packet protocol; receive a response message indicating rejection of the request, and upon detecting that a field in the response message defines a reason other than the part of the wireless cellular network does not support first and second versions of the packet protocol on a single channel, to default to transmit a default request message to request establishment of a channel to access the packet-based network, the default request message requests the channel as being of a type that supports the first version of the packet protocol.

Abstract: A process for manufacturing a printed circuit board having high-density microvias formed in a thick substrate is disclosed. The method includes the steps of forming one or more holes in a thick substrate using a laser drilling technique, electroplating the one or more holes with a conductive material, wherein the conductive material does not completely fill the one or more holes, and filling the one or more plated holes with a non-conductive material.

Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

Abstract: A system and method are provided for regulating a voltage level at a load. The method configures a current control mechanism to generate a current through a first inductor and a second inductor that are coupled in series and configures a voltage control mechanism to provide a portion of the current to regulate the voltage level. The second inductor isolates the load from a parasitic capacitance of the current control mechanism. An electric power conversion device for regulating the voltage level at the load comprises the current control mechanism that is coupled to an electric power source and configured to generate a current through the first inductor and the second inductor that are coupled in series and the voltage control mechanism that is coupled to the second inductor and configured to provide a portion of the current to regulate the voltage level.

Abstract: A system and method for calibrating an integrated circuit. The method includes configuring a first impedance for a first output of the integrated circuit according to a first configuration code and measuring a first voltage at the first output which corresponds to the first configuration code. The method further includes configuring a second impedance for a second output of the integrated circuit according to a second configuration code and measuring a second voltage at the second output which corresponds to the second configuration code. A determination of which of the first voltage and the second voltage is nearest to a predetermined voltage value. Based on the voltage determination, the integrated circuit is configured according a code of said first and second codes that corresponds to the voltage nearest to the predetermined voltage.

Abstract: A system, method, and computer program product are provided for determining a size of an attribute storage buffer. Input attributes read by a shader program to generate output attributes are identified. A portion of the output attributes to be consumed by a destination shader program is identified. The size of the attribute storage buffer that is allocated for execution of the shader program is computed based on the input attributes and the portion of the output attributes.

Abstract: A system, method, and computer program product are provided for GPU demand paging. In operation, input data is addressed in terms of a virtual address space. Additionally, the input data is organized into one or more pages of data. Further, the input data organized as the one or more pages of data is at least temporarily stored in a physical cache. In addition, access to the input data in the physical cache is facilitated.

Abstract: A system, method, and computer program product are provided for distributed processing of overlapping portions of pixels. In use, a plurality of pixels to be processed utilizing a plurality of display processing modules across a plurality of interfaces are identified. Additionally, the pixels are apportioned into a plurality of overlapping portions of the pixels in accordance with a number of the display processing modules and display interfaces. Further, processing of the overlapping portions of the pixels is distributed across the display processing modules and the display interfaces in such way that the portions can be recombined into a single contiguous final image by a plurality display controllers.

Abstract: The disclosure provides for an SRAM array having a plurality of wordlines and a plurality of bitlines, referred to generally as SRAM lines. The array has a plurality of cells, each cell being defined by an intersection between one of the wordlines and one of the bitlines. The SRAM array further includes voltage boost circuitry operatively coupled with the cells, the voltage boost circuitry being configured to provide an amount of voltage boost that is based on an address of a cell to be accessed and/or to provide this voltage boost on an SRAM line via capacitive charge coupling.

Abstract: A method and a system are provided for performing address-based memory access assist. An address is received for a memory access and a determination is made, based on the address, that access assist is enabled for at least one storage cell corresponding to the address. The access assist is applied to the at least one storage cell to perform the memory access.

Abstract: A processor and a circuit implementing a continuous-time deglitching technique for a digital-to-analog converter are disclosed. The circuit includes a digital-to-analog converter having a differential current output, an operational amplifier having an inverting input coupled to a first output of the differential current output and a non-inverting input coupled to a second output of the differential current output, and a transistor coupled to the second output and the output of the operational amplifier. The operational amplifier is configured to operate the transistor to adjust the voltage potential of the second output to substantially match the voltage potential of the first output.

Abstract: One embodiment of the present invention sets forth a technique for stroking rendered paths. Path rendering may be accelerated when a graphics processing unit or other processor is configured to identify pixels that are within half of the stroke width of any point along a path to be stroked. The path is represented by quadratic Bèzier segments and a cubic equation is evaluated to determine whether or not each point in a conservative hull that bounds the quadratic Bèzier segment is within the stroke width.

Abstract: A method and system for accessing content on demand are described. In one embodiment, upon receiving a user request to access an instance of content (e.g., information that is independent of a particular physical medium), the identity of the user is authenticated. The request conveys a unique identifier of the instance of content and a key for activating the content corresponding thereto according to an instance of ownership stored therewith. The instance of ownership corresponding to the user in that instance of content is ascertained. Upon associating the instance of ownership corresponding to the user in the instance of content, the instance of content is activated to allow the user to access the instance of content according to the corresponding instance of ownership. Where access is demanded in excess of the instance of ownership, a transaction is initiated with which the instance of ownership can be upgraded.