Patents Assigned to NVidia
  • Patent number: 8804437
    Abstract: A column select multiplexer, a method of reading data from a random-access memory and a memory subsystem incorporating the multiplexer or the method. In one embodiment, the column select multiplexer includes: (1) a first field-effect transistor having a gate coupled via an inverter to a bitline of a static random-access memory array, (2) a second field-effect transistor coupled in series with the first field-effect transistor and having a gate coupled to a column select bus of the static random-access memory array and (3) a latch having an input coupled to the first and second field-effect transistors.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: August 12, 2014
    Assignee: Nvidia Corporation
    Inventors: Andreas Gotterba, Joel DeWitt, Marek Smoszna
  • Patent number: 8803879
    Abstract: An invention is provided for rendering using an omnidirectional light. A shadow cube texture map having six cube faces centered by a light source is generated. Each cube face comprises a shadow texture having depth data from a perspective of the light source. In addition, each cube face is associated with an axis of a three-dimensional coordinate system. For each object fragment rendered from the camera's perspective a light-to-surface vector is defined from the light source to the object fragment, and particular texels within particular cube faces are selected based on the light-to-surface vector. The texel values are tested against a depth value computed from the light to surface vector. The object fragment is textured as in light or shadow according to the outcome of the test.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: August 12, 2014
    Assignee: Nvidia Corporation
    Inventors: William P. Newhall, Jr., Mark J. Kilgard
  • Patent number: 8804580
    Abstract: An apparatus, such as a base station, transmitting signaling information in a cellular communication system whereby a plurality of shared uplink transmission resources is divided into sets of mutually exclusive transmission resources. The apparatus comprises means for granting uplink resources to a wireless subscriber communication unit via a grant message for uplink transmission; means for receiving an uplink transmission from a wireless subscriber communication unit; means for deriving an uplink code resource identifier from the uplink transmission or the grant message; means for assigning at least one downlink code sequence used to carry downlink signaling information associated with the uplink transmission and which is derived using the uplink code resource identifier; and means for transmitting a downlink transmission comprising the at least one downlink code sequence to the wireless subscriber communication unit.
    Type: Grant
    Filed: October 18, 2010
    Date of Patent: August 12, 2014
    Assignee: Nvidia Corporation
    Inventor: Nicholas William Anderson
  • Patent number: 8806100
    Abstract: Circuits, methods, and apparatus that reduce the power consumed by transactions initiated by a number of USB host controllers. Peripheral devices on a number of USB networks are accessed in a coordinated manner in order to reduce power dissipated by a CPU and other circuits when reading data needed by the host controllers. The resulting memory reads are temporally clustered. This allows the CPU to process a greater number of requests each time it leaves a low-power state. As a result, the CPU may possibly remain in a sleep state for a longer period of time, thus saving power. This is accomplished at the host controller level by synchronizing the time frames used by each host controller in a system. The synchronizing signal may be one or more bits of a frame count provided by one host controller to a number of other frame controllers.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: August 12, 2014
    Assignee: NVIDIA Corporation
    Inventors: John Berendsen, Robert Chapman
  • Publication number: 20140219007
    Abstract: This description is directed to a dynamic random access memory (DRAM) array having a plurality of rows and a plurality of columns. The array further includes a plurality of cells, each of which are associated with one of the columns and one of the rows. Each cell includes a capacitor that is selectively coupled to a bit line of its associate column so as to share charge with the bit line when the cell is selected. There is a segmented word line circuit for each row, which is controllable to cause selection of only a portion of the cells in the row.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA Corporation
    Inventor: William James Dally
  • Publication number: 20140223420
    Abstract: A basic block within a thread program is characterized for convergence based on mapping the basic block to an indicator subnet within a corresponding Petri net generated to model the thread program. Each block within the thread program may be similarly characterized. Each corresponding Petri net is enumerated to generate a corresponding state space graph. If the state space graph includes an exit node with an odd execution count attribute, such as by Petri net coloring, then the corresponding basic block is divergent. The corresponding basic block is convergent otherwise. Using this characterization technique, a thread program compiler may advantageously identify all convergent blocks within a thread program and apply appropriate optimizations to the convergent blocks.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Manjunath Kudlur
  • Publication number: 20140218390
    Abstract: A system, method, and computer program product are provided for anti-aliasing. During a first processing pass of a plurality of graphics primitives, z data is computed for multiple samples of each pixel in an image to generate a multi-sample z buffer. During a second processing pass of the graphics primitives, computed color values corresponding to each pixel in a color buffer that stores one color value for each pixel are accumulated.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Christian Jean Rouet, Eric Brian Lum, Rui Manuel Bastos
  • Publication number: 20140221087
    Abstract: A gaming console including a housing configured for handheld manipulation. A processor is contained within the housing and configured for executing a gaming application. Memory is contained within the housing and configured for storing executables of the gaming application. At least one control button is exposed on the housing and is configured for receiving input from a user that provides an instruction for the gaming application. The gaming console includes a high definition (HD) display for displaying the gaming application.
    Type: Application
    Filed: November 27, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA Corporation
    Inventors: Jen-Hsun HUANG, Anthony Michael TAMASI, Franck DIARD
  • Publication number: 20140218084
    Abstract: An approach is provided for modulating an input clock signal of a clock source. In one example, a modulated clock device receives the input clock signal from the clock source, applies a sequence of digital delay devices to the input clock signal to generate one or more delayed phases of the input clock signal, sends the input clock signal and the one or more delayed phases of the input clock signal to an output phase multiplexer, selects an appropriate phase of the input clock signal from among the input clock signal and the one or more delayed phases of the input clock signal, and generates an output clock signal based on the appropriate phase of the input clock signal.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Tom J. VERBEURE
  • Publication number: 20140218787
    Abstract: A display panel is provided that includes a plurality of pixel units, each having a first surface and a second surface opposite to the first surface, and comprising an electrophoretic gel part with a shape tapered in a direction from the first surface to the second surface, wherein a top surface of the electrophoretic gel part forms the first surface and electrophoretic particles are provided in the electrophoretic gel part; a light guiding part with a shape tapered in a direction from the second surface to the first surface, wherein the light guiding part and the electrophoretic glue part match in shape and abut with each other, and a bottom surface of the light guiding part forms at least a portion of the second surface; and a light-emitting device provided on the bottom surface of the light guiding part and operable to emit light toward the first surface.
    Type: Application
    Filed: September 5, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA Corporation
    Inventor: Shuang Xu
  • Publication number: 20140218379
    Abstract: A device, system and method for transferring network data are presented. The device includes: a data processing module configured to convert a data signal in a TMDS signal output via a DVI of a graphics card to network data for being transferred via a network; and a network transmitter for receiving the network data and transferring the network data to an external device via the network. The data signal is generated by encoding texture data generated by a GPU of the graphics card by a digital video sender of the graphics card. The texture data is generated by binding a pointer to general computing data stored in a device memory of the graphics card to a texture stored in the device memory by the GPU. The general computing data is generated by general computation executed by the GPU.
    Type: Application
    Filed: April 25, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: ZHEN JIA, Shu ZHANG, Jun QIU
  • Publication number: 20140218332
    Abstract: A flat panel electronic device is presented. The flat panel electronic device comprises an actuating apparatus, a supporting apparatus and a control apparatus. The actuating apparatus is configured to generate a first actuating signal. The supporting apparatus has an extending position and an initial position, wherein the supporting apparatus is configured to support at least a portion of the flat panel electronic device to a predetermined height when the supporting apparatus is in the extending position. The control apparatus is configured to control the movement of the supporting apparatus in response to the first actuating signal. In addition, the supporting apparatus can also have an additional function for adjusting the angle of the display panel of the flat panel electronic device with respect to the user, so as to improve the comfort level for watching.
    Type: Application
    Filed: April 17, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: MINGYI YU
  • Publication number: 20140218376
    Abstract: A system and method for image processing are provided. The system comprises a main computing device and a secondary computing device. The main computing device comprises a main graphics card and a main central processing unit, and the secondary computing device comprises a secondary graphics card and a secondary central processing unit. The main computing device is configured to detect the secondary computing device. The main central processing unit is configured to send a request to process raw image data together to the secondary central processing unit and allocate the raw image data to the main graphics card and the secondary graphics card after receiving a response from the secondary central processing unit. The main graphics card and the secondary graphics card are configured to process images based on the allocation of the main central processing unit.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 7, 2014
    Applicant: NVIDIA Corporation
    Inventor: Maojiang (Jacen) LIN
  • Publication number: 20140221054
    Abstract: Saving power in a mobile terminal includes determining alignment processing moments after the mobile terminal enters a standby mode. Alignable wakeup events, which occur during alignment processing periods corresponding to each alignment processing moment, are thus controlled to commence related processing at each of the alignment processing moments. Power consumption caused by various wakeup events in a standby mode may thus be reduced and battery life of the mobile terminal may thus be improved.
    Type: Application
    Filed: December 2, 2013
    Publication date: August 7, 2014
    Applicant: Nvidia Corporation
    Inventors: Li LIN, Jiukai MA, Haonong YU, Jun QIU, Liangchuan MI, Shail DAVE, Zhichao ZU, Karthik SAMYNATHAN, Richard CLARK
  • Publication number: 20140218001
    Abstract: A system and method are provided for generating non-overlapping enable signals. A peak voltage level is measured at an output of a current source that is configured to provide current to a voltage control mechanism. The non-overlapping enable signals are generated for the voltage control mechanism based on the peak voltage level. A system includes the current source, a downstream controller, and the voltage control mechanism that is coupled to the load. The current source is configured to provide current to the voltage control mechanism. The controller is configured to measure the peak voltage level at the output of the current source and generate the non-overlapping enable signals based on the peak voltage level. The non-overlapping enable signals provide a portion of the current to the load.
    Type: Application
    Filed: February 5, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: William J. Dally
  • Publication number: 20140223221
    Abstract: A modulated clock device is provided that includes an update device for updating a phase of the modulated clock device. In one example, the update device includes an update phase multiplexer coupled to an output phase multiplexer of an output clock generator and configured to receive an input clock signal and one or more phases of the input clock signal; an output phase fractional counter coupled to the update phase multiplexer and configured to receive an update clock signal and to generate an output phase; and an update phase device coupled to the output phase fractional counter and to the update phase multiplexer. The output phase fractional counter is further configured to send the output phase to the output phase multiplexer and to the update phase device. The update phase device is configured to generate an update phase and to send the update phase to the update phase multiplexer.
    Type: Application
    Filed: February 6, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Tom J. VERBEURE
  • Publication number: 20140219482
    Abstract: A flat panel electronic device and an audio playing apparatus thereof are provided. The audio playing apparatus comprises an audio generator, a plurality of speakers, a sensor and a controller. The audio generator is operable to generate a left channel audio and a right channel audio. The plurality of speakers are configured such that at least one pair of speakers is symmetrically disposed at a left side and a right side of the flat panel electronic device no matter how the flat panel electronic device is placed. The sensor is operable to detect a placed state of the flat panel electronic device in the installed state. The controller is operable to receive a detecting signal from the sensor so as to control the at least one pair of speakers to play the left channel audio and the right channel audio correspondingly according to the placed state of the flat panel electronic device.
    Type: Application
    Filed: April 17, 2013
    Publication date: August 7, 2014
    Applicant: Nvidia Corporation
    Inventor: Nvidia Corporation
  • Publication number: 20140223219
    Abstract: A clock frequency controller for a processor and a method of operation thereof. The clock frequency controller may be embodied in a processor, including: (1) a processing core operable at a clock frequency to undertake a processing of a graphics application, and (2) a clock frequency controller coupled to the processing core and operable to adjust the clock frequency based on a current frame rate of the processing and a target frame rate for the processing.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 7, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Ilan Aelion, Aleksandr Frid, Satya Popuri
  • Publication number: 20140223236
    Abstract: A device for testing a graphics card is presented. The device includes a core test apparatus. The core test apparatus includes a processor configured to perform a test operation on a graphics card and a power interface for transferring electric energy to the core test apparatus. Using the device for testing a graphics card provided by the present invention makes a graphics card test easier and more efficient.
    Type: Application
    Filed: February 7, 2014
    Publication date: August 7, 2014
    Applicant: NVIDIA Corporation
    Inventors: Dongbo HAO, Tiecheng LIANG, Jie ZHOU
  • Patent number: 8797340
    Abstract: A system, method, and computer program product are provided for modifying a pixel value as a function of a display duration estimate. In use, a value of a pixel of an image frame to be displayed on a display screen of a display device is identified, wherein the display device is capable of handling updates at unpredictable times. Additionally, the value of the pixel is modified as a function of an estimated duration of time until a next update including the pixel is to be displayed on the display screen. Further, the modified value of the pixel is transmitted to the display screen for display thereof.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: NVIDIA Corporation
    Inventors: Gerrit A. Slavenburg, Tom Verbeure, Robert Jan Schutten