Abstract: A tessellation pipeline includes an alpha phase and a beta phase. The alpha phase includes pre-tessellation processing stages, while the beta phase includes post-tessellation processing stages. A processing unit configured to implement a processing stage in the alpha phase stores input graphics data within a buffer and then copies over that buffer with output graphics data, thereby conserving memory resources. The processing unit may also copy output graphics data directly to a level 2 (L2) cache for beta phase processing by other tessellation pipelines, thereby avoiding the need for fixed function copy-out hardware.

Abstract: Embodiments of the approaches disclosed herein include a subsystem that includes an access tracking mechanism configured to monitor access operations directed to a first memory and a second memory. The access tracking mechanism detects an access operation generated by a processor for accessing a first memory page residing on the second memory. The access tracking mechanism further determines that the first memory page is included in a first subset of memory pages residing on the second memory. The access tracking mechanism further locates, within a reference vector, a reference bit that corresponds to the first memory page, and sets the reference bit. One advantage of the present invention is that memory pages in a hybrid system migrate as needed to increase overall memory performance.

Abstract: The disclosure provides a micro-processing system operable in a hardware decoder mode and in a translation mode. In the hardware decoder mode, the hardware decoder receives and decodes non-native ISA instructions into native instructions for execution in a processing pipeline. In the translation mode, native translations of non-native ISA instructions are executed in the processing pipeline without using the hardware decoder. The system includes a code portion profile stored in hardware that changes dynamically in response to use of the hardware decoder to execute portions of non-native ISA code. The code portion profile is then used to dynamically form new native translations executable in the translation mode.

Abstract: A system, method, and computer program product are provided for applying a callback function to data values. In use, a plurality of data values and a callback function are identified. Additionally, the callback function is recursively applied to the plurality of data values in order to determine a result. Further, the result is returned.

Abstract: One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a first graphics primitive intersects a voxel and calculating a first set of coefficients associated with a first plane defined by the intersection of the first graphics primitive and the voxel. The technique further involves determining that a second graphics primitive intersects the voxel and calculating a second set of coefficients associated with a second plane defined by the intersection of the second graphics primitive and the voxel. The technique further involves calculating a third set of coefficients associated with a third surface based on the first set of coefficients and the second set of coefficients. The technique further involves calculating at least one of an amount of the voxel that is located on the back side of the third surface and an occlusion value based on the third set of coefficients.

Abstract: A system, method, and computer program product are provided for processing graphics data associated with shading. In operation, a first fragment is received. Further, the first fragment is shaded. While the first fragment is being shaded, a second fragment is received and it is determined whether at least one aspect of the second fragment conflicts with the first fragment. If it is determined that the at least one aspect of the second fragment does not conflict with the first fragment, the second fragment is shaded. If it is determined that the at least one aspect of the second fragment conflicts with the first fragment, information associated with the second fragment is stored, a third fragment is received, and the third fragment is shaded, if it is determined that at least one aspect of the third fragment does not conflict with the first fragment.

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract: One embodiment of the present invention includes techniques for a first processing unit to perform an atomic operation on a memory page shared with a second processing unit. The memory page is associated with a page table entry corresponding to the first processing unit. Before executing the atomic operation, an MMU included in the first processing unit evaluates an atomic permission bit that is included in the page table entry. If the MMU determines that the atomic permission bit is inactive, then the two processing units coordinate to change the permission status of the memory page. As part of the status change, the atomic permission bit in the page table entry is activated. Subsequently, the first processing unit performs the atomic operation uninterrupted by the second processing unit. Advantageously, coordinating the processing unit via the atomic permission bit ensures the proper and efficient execution of the atomic operation.

Abstract: A system and apparatus that include a selectable synchronizer circuit for synchronizing data across asynchronous boundaries are disclosed. The apparatus includes a unit associated with a first clock domain and a synchronizer sub-unit (SSU) coupled to the unit and associated with a second clock domain. The synchronizer sub-unit includes two or more synchronizers and selector logic configured to select one output of the two or more synchronizers.

Abstract: A quality of service (QoS) management server and a method of managing QoS. One embodiment of the QoS management server, includes: (1) a network interface controller (NIC) configured to receive QoS statistics indicative of conditions of a network over which rendered video is transmitted, the rendered video having a fidelity and a latency, and (2) a graphics processing unit (GPU) operable to employ said QoS statistics to tune said fidelity to affect said latency.

Abstract: A system, method, and computer program product are provided for creating a hardware design. In use, one or more parameters are received, where at least one of the parameters corresponds to an interface protocol. Additionally, a data flow is constructed based on the one or more parameters. Further, an indication of one or more control constructs is received, where a hardware design is capable of being created, utilizing the constructed data flow and the one or more control constructs.

Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.

Abstract: A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing.

Abstract: A method for producing candidate fault circuitry in an integrated circuit (IC) is disclosed. The method comprises tracing back from at least one failing output of the IC to determine a corresponding fan-in cone for each failing output using simulation values obtained from a fault free simulation of a design of the IC. Further, it comprises determining a first set of suspect fault candidates for each failing output, wherein each suspect fault candidate potentially corresponds to a defective element in the IC. Next, it comprises tracing forward from each suspect in the first set to determine a second set of suspects, which is a narrower subset of the first set. Finally, it comprises identifying a failing block from the IC design, wherein the failing block comprises suspect fault candidates from the second set and can be simulated independently of the full design.

Abstract: Power management systems and methods that facilitate efficient and effective power conservation are presented. In one embodiment a power management method comprises: performing an initiation metric determination process, and adjusting operations of a logic component based on said threshold value. In one exemplary implementation, the initiation metric determination process includes monitoring activity of a logic component, and establishing a power conservation initiation threshold value. The initiation metric determination process can include performing a system architecture characteristic analysis in which a system architecture power-consumption break-even time (BE) is determined for the system. The initiation metric determination process can also include performing a system utilization analysis process is performed in which idle period durations detected during said monitoring are sorted into a variety of different length intervals and analyzed accordingly.

Abstract: A Multi-configuration Processor-Memory device for coupling to a PCB (printed circuit board) interface. The device comprises a substrate that supports multiple configurations of memory components and a processor while having a single, common interface with a PCB interface of a printed circuit board. In a first configuration, the substrate supports a processor and a first number of memory components. In a second configuration, the substrate supports a processor and an additional number of memory components. The memory components can be pre-tested, packaged memory components mounted on the substrate. The processor can be a surface mounted processor die. Additionally, the processor can be mounted in a flip chip configuration, side-opposite the memory components. In the first configuration, a heat spreader can be mounted on the memory components and the processor to dissipate heat.

Abstract: An approach is disclosed for performing initialization operations for a graphics processing unit (GPU). The approach includes detecting errors while performing one or more initialization operations. Further, the approach includes releasing a holdoff on a communication link that couples the GPU to a memory bridge and causing debug output to be displayed to a user that indicates the error.

Abstract: A method and system are implemented for monitoring the thermal dissipation from a computer processing unit. The system comprises a temperature sensor, and a temperature controller. The temperature controller is configured to set a temperature observation window in a first temperature range, gradually narrow the observation window from the first temperature range after a monitored temperature of the processing unit has entered the observation window, and issue an alert signal when the monitored temperature exits the observation window.

Abstract: In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction, and execution logic configured to receive the plurality of operands and the multiply operation. The execution logic includes a first logic path configured to perform the multiply operation on the plurality of operands and output a result, and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation.

Abstract: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.