Abstract: Computing devices are now used for various purposes ranging from monitoring a refrigerator to driving automobiles. Protecting the data and logic within the chips of the computing devices is essential to ensure reliable operation. When a particular partition of a chip is powered-up but the logic of the partition is not reset, the logic will be in an unpredictable random state. To operate in a secure environment, it is necessary to start the operation of the logic from a known state and not a random state. To ensure the logic is operating in a secure environment, a digital reset detector circuit (DRDC) is provided that indicates if the logic was reset after power-up. The DRDC can ensure chips are secure from attacks involving reset deprivation upon power-up and help protect various secure and secret assets in a chip, including customer keys.

Abstract: A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided.

Abstract: One aspect of the disclosure provides a method for rendering an image. The method includes: placing primitives of the image in a screen space; binning the primitives into tiles of the screen space that the primitives touch; and rasterizing the tiles at one tile of the tiles at a time. The aforementioned rasterizing includes shading a subset of the primitives binned to the one tile at a first shading rate during a first pass and shading the subset of primitives binned to the one tile at a second shading rate during a second pass, the second shading rate is different from the first shading rate, and the aforementioned placing is performed once while the image is rendered.

Abstract: A system, method, and computer program product are provided for simultaneously determining settings for a plurality of parameter variations. In use, a plurality of parameter variations associated with a device is identified, where the plurality of parameter variations are organized into a plurality of segments. Additionally, settings for each of the plurality of parameter variations are determined and consistency of the settings across the plurality of segments is ensured.

Abstract: A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.

Abstract: A method, computer readable medium, and system are disclosed for gaze tracking. The method includes the steps of receiving reflected light rays at an optical sensor, where all of the reflected light rays converge towards a rotational center of an eye and generating pattern data based on intersections of the reflected light rays at a surface of the optical sensor. A processor computes an estimated gaze direction of the eye based on the pattern data.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: Aspects of the present invention are directed to techniques for improving the efficiency of power supply schemes by continuously and adaptively scaling voltage and frequency levels in an integrated circuit based on measured conditions in real-time, without resorting to a reliance on excessive pre-computed margins typical of conventional schemes. Embodiments of the present invention employ a self-tuning dynamic voltage control oscillator (or other similar clock signal generator) that sets the frequency for components in the integrated circuit. When a requested frequency exceeds a maximum allowed frequency for a given voltage level (accounting for other age and temperature related conditions), a look-up table is dynamically referenced to determine a new voltage level that is sufficient to safely and efficiently generate the requested frequency.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: A method for displaying a near-eye light field display (NELD) image is disclosed. The method comprises determining a pre-filtered image to be displayed, wherein the pre-filtered image corresponds to a target image. It further comprises displaying the pre-filtered image on a display. Subsequently, it comprises producing a near-eye light field after the pre-filtered image travels through a microlens array adjacent to the display, wherein the near-eye light field is operable to simulate a light field corresponding to the target image. Finally, it comprises altering the near-eye light field using at least one converging lens, wherein the altering allows a user to focus on the target image at an increased depth of field at an increased distance from an eye of the user and wherein the altering increases spatial resolution of said target image.

Abstract: An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.

Abstract: A circuit, method, and system are disclosed for sampling a signal. The system includes a sampler circuit configured to sample input signals when a clock signal is at a first voltage level to produce sampled signals, a detection circuit that is coupled to the sampler circuit, and a feedback circuit that receives an output signal and generates the clock signal. The detection circuit pre-charges the sampled signals when the clock signal is at a second voltage level and, using threshold adjusted inverters, detects voltage levels of each sampled signal to produce detected voltage levels, where a threshold voltage of the threshold adjusted inverters is entirely outside of a transition voltage range of the sampler circuit. In response to one of the detected voltage levels transitioning from the second level to the first level, the detection circuit transitions the output signal from the first voltage level to the second voltage level.

Abstract: A system and method for procedurally synthesizing a training dataset for training a machine-learning model. In one embodiment, the system includes: (1) a training designer configured to describe variations in content of training images to be included in the training dataset and (2) an image definer coupled to the training designer, configured to generate training image definitions in accordance with the variations and transmit the training image definitions: to a 3D graphics engine for rendering into corresponding training images, and further to a ground truth generator for generating associated ground truth corresponding to the training images, the training images and the associated ground truth comprising the training dataset.

Abstract: Improved methods and systems for accessing a memory in a computer are disclosed. In one embodiment, the true and complement portions of a differential write clock signal are employed as two single ended clock signals for independently controlling different memory chips in a memory system. For example, in a memory system having two memory chips, one memory chip is configured to use the true write clock signal and the other memory chip is configured to use the complement write clock signal. Employing the differential write clock signal as two single ended clock signals allows overlapping of write and read operations across multiple memory chips, reducing the time needed for accessing memory. Accordingly, the disclosed methods and systems provide a more efficient memory system that can be used to improve the operation of a computer.

Abstract: A method, computer readable medium, and system are disclosed for generating mixed-primary data for display. The method includes the steps of receiving a source image that includes a plurality of pixels, dividing the source image into a plurality of blocks, analyzing the source image based on an image decomposition algorithm, encoding chroma information and modulation information to generate a video signal, and transmitting the video signal to a mixed-primary display. The chroma information and modulation information correspond with two or more mixed-primary color components and are generated by the image decomposition algorithm to minimize error between a reproduced image and the source image. The two or more mixed-primary colors selected for each block of the source image are not limited to any particular set of colors and each mixed-primary color component may be selected from any color capable of being reproduced by the mixed-primary display.

Abstract: Embodiments of the claimed subject matter provide systems and methods for configuring and connecting a controller to a game streaming service. The system includes a plurality of input controls and a network controller configured for communicating with a game streaming service. The system further includes a processor coupled to the plurality of input controls and the network controller. The processor is configured communicate with the game streaming service to login to a game streaming service account and communicate input from the plurality of controls to the game streaming service. The system further includes a power source configured to provide power to the plurality of input controls, the network controller, and the processor.

Abstract: Embodiments related to selecting a runahead poison policy from a plurality of runahead poison policies during microprocessor operation are provided. The example method includes causing the microprocessor to enter runahead upon detection of a runahead event and implementing a first runahead poison policy selected from a plurality of runahead poison policies operative to manage runahead poison injection during runahead. The example method also includes during microprocessor operation, selecting a second runahead poison policy operative to manage runahead poison injection differently from the first runahead poison policy.

Abstract: In embodiments of the invention, an apparatus may include a display comprising a plurality of pixels. The apparatus may further include a computer system coupled with the display and operable to instruct the display to display a deconvolved image corresponding to a target image, wherein when the display displays the deconvolved image while located within a near-eye range of an observer, the target image may be perceived in focus by the observer.