Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

Abstract: Convergence of threads executing common code sections is facilitated using instructions inserted at strategic locations in computer code sections. The inserted instructions enable the threads in a warp or other group to cooperate with a thread scheduler to promote thread convergence.

Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

Abstract: A hardware-based traversal coprocessor provides acceleration of tree traversal operations searching for intersections between primitives represented in a tree data structure and a ray. The primitives may include opaque and alpha triangles used in generating a virtual scene. The hardware-based traversal coprocessor is configured to determine primitives intersected by the ray, and return intersection information to a streaming multiprocessor for further processing. The hardware-based traversal coprocessor is configured to omit reporting of one or more primitives the ray is determined to intersect. The omitted primitives include primitives which are provably capable of being omitted without a functional impact on visualizing the virtual scene.

Abstract: A system and method of rendering a fluid-like object in a volume space are provided. In one embodiment, the method includes: (1) determining a list of bricks in the volume space that the fluid-like object would occupy, (2) grouping the bricks into buckets based on depth values of the bricks and (3) rendering each of the buckets separately.

Abstract: A method, computer readable medium, and system are disclosed for redirecting a user's movement through a physical space while the user views a virtual environment. A temporary visual suppression event is detected when a user's eyes move relative to the user's head while viewing a virtual scene displayed on a display device, an orientation of the virtual scene relative to the user is modified to direct the user to physically move along a planned path through a virtual environment corresponding to the virtual scene, and the virtual scene is displayed on the display device according to the modified orientation.

Abstract: A fan control module configured to control the speed of a fan receives a signal that indicates the power used by a graphics processing unit (GPU) and a signal that indicates the GPU temperature. Whenever the GPU power exceeds a power threshold level, but the GPU temperature is below a temperature threshold level, the control module turns the fan on and causes the fan to operate at a minimum speed. Whenever the GPU temperature is above the temperature threshold, the control module causes the fan speed to increase with increasing temperature, regardless of power. The control module turns the fan off only when both the GPU temperature is below the temperature threshold and the GPU power is below the power threshold. Although the algorithm is discussed in conjunction with a GPU, the algorithm can be implemented with any type of processor or subsystem that needs to be fan-cooled.

Abstract: A method, computer readable medium, and system are disclosed for performing stable ray tracing.

Abstract: A method, computer readable medium, and system are disclosed for computing a path for a user to move along within a physical space while viewing a virtual environment in a virtual reality system. A path for a user to physically move along through a virtual environment is determined based on waypoints and at least one characteristic of the physical environment within which the user is positioned, position data for the user is received indicating whether and how much a current path taken by the user has deviated from the path, and an updated path is computed through the virtual environment based on the waypoints and the at least one characteristic of the physical environment.

Abstract: A method of adjusting a shading normal vector for a computer graphics rendering program. Calculating a normalized shading normal vector pointing outwards from an origin point on a tessellated surface modeling a target surface to be rendered. Calculating a normalized outgoing reflection vector projecting from the origin point for an incoming view vector directed towards the origin point and reflecting relative to the normalized shading normal vector. Calculating a correction vector such that when the correction vector is added to the normalized outgoing reflection vector a resulting vector sum is yielded that is equal to a maximum reflection vector, wherein the maximum reflection vector is on or above the tessellated surface. Calculating a normalized maximum reflection vector by normalizing a vector sum of the correction vector plus the maximum reflection vector.

Abstract: A system, method, and computer readable medium for inverse graphics rendering comprise a differentiable rendering pipeline and a gradient descent optimization engine. A given scene is described using scene parameters. Visibility functions, and other rendered functions, are constructed to be continuous and differentiable, allowing the optimization engine and the rendering pipeline to efficiently iterate through increasingly refined scene models.

Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

Abstract: A method, computer readable medium, and system are disclosed for training a neural network. The method includes the steps of selecting an input sample from a set of training data that includes input samples and noisy target samples, where the input samples and the noisy target samples each correspond to a latent, clean target sample. The input sample is processed by a neural network model to produce an output and a noisy target sample is selected from the set of training data, where the noisy target samples have a distribution relative to the latent, clean target sample. The method also includes adjusting parameter values of the neural network model to reduce differences between the output and the noisy target sample.

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

Abstract: A system for, and method of, computing reduced-resolution indirect illumination using interpolated directional incoming radiance and a graphics processing subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cone tracing shader executable in a graphics processing unit to compute directional incoming radiance cones for sparse pixels and project the directional incoming radiance cones on a basis and (2) an interpolation shader executable in the graphics processing unit to compute outgoing radiance values for untraced pixels based on directional incoming radiance values for neighboring ones of the sparse pixels.

Abstract: A graphics server and method for streaming rendered content via a remote graphics rendering service is provided. In one embodiment, the server includes a memory, a graphics renderer, a frame capturer, an encoder, and a processor. The memory is configured to store a pre-computed skip-frame message indicative to a client to re-use a previously transmitted frame of the video stream. The graphics renderer is configured to identify when rendered content has not changed. When the graphics renderer identifies that the rendered content has not changed, the processor is configured to cause: (1) the frame capturer to not capture the frames of the rendered content; (2) the encoder to not encode the frames of the rendered content; and (3) the pre-encoded skip-frame message to be transmitted without requiring any pixel processing.

Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

Abstract: In one embodiments, a system comprises: a plurality of scan test chains configured to perform test operations at a first clock speed; a central test controller for controlling testing by the scan test chains; and an interface configured to generate instructions to direct central test controller. The interface communicates with the centralized test controller at the first clock speed and an external scan input at a second clock speed. The second clock speed can be faster than the first clock speed. The instructions communicated to the central controller can be directions associated with sequential scan compression/decompression operations. In one exemplary implementation, the interface further comprise a mode state machine used to generate the mode control instructions and a test register state machine that generate test state control instructions, wherein the test mode control instructions and the test state control instructions direct operations of the centralized test controller.

Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one exemplary implementation, an address allocation process comprises: establishing space for managed pointers across a plurality of memories, including allocating one of the managed pointers with a first portion of memory associated with a first one of a plurality of processors; and performing a process of automatically managing accesses to the managed pointers across the plurality of processors and corresponding memories. The automated management can include ensuring consistent information associated with the managed pointers is copied from the first portion of memory to a second portion of memory associated with a second one of the plurality of processors based upon initiation of an accesses to the managed pointers from the second one of the plurality of processors.