Abstract: One embodiment of the present invention is a computer-implemented method for scheduling a thread group for execution on a processing engine that includes identifying a first thread group included in a first set of thread groups that can be issued for execution on the processing engine, where the first thread group includes one or more threads. The method also includes transferring the first thread group from the first set of thread groups to a second set of thread groups, allocating hardware resources to the first thread group, and selecting the first thread group from the second set of thread groups for execution on the processing engine. One advantage of the disclosed technique is that a scheduler only allocates limited hardware resources to thread groups that are, in fact, ready to be issued for execution, thereby conserving those resources in a manner that is generally more efficient than conventional techniques.

Abstract: A queue manager apparatus converts inbound commands of a first width into scalar format commands to be queued in a command queue. Furthermore, the queue manager converts the scalar format commands residing in the command queue into outbound commands of a second width for transmission. Converting inbound commands to scalar format commands and then converting the scalar format commands to a target width for transmission allows the queue manager to advantageously provide efficient and programmable command transmission between arbitrary processing units, regardless of potentially mismatched native command widths.

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

Abstract: A PAM-4 communication process divides a full burst of raw data into two half bursts, extracts a bit from each half burst and communicating the extracted bit on a DBI line, and encodes the remaining bits of the half burst to avoid maximum transitions between PAM-4 symbols on a data line.

Abstract: A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.

Abstract: An apparatus and method for radar based gesture detection. The apparatus includes a processing element and a transmitter configured to transmit radar signals. The transmitter is coupled to the processing element. The apparatus further includes a plurality of receivers configured to receive radar signal reflections, where the plurality of receivers is coupled to the processing element. The transmitter and plurality of receivers are configured for short range radar and the processing element is configured to detect a hand gesture based on the radar signal reflections received by the plurality of receivers.

Abstract: A method, computer readable medium, and system are disclosed for generating a Gaussian mixture model hierarchy. The method includes the steps of receiving point cloud data defining a plurality of points; defining a Gaussian Mixture Model (GMM) hierarchy that includes a number of mixels, each mixel encoding parameters for a probabilistic occupancy map; and adjusting the parameters for one or more probabilistic occupancy maps based on the point cloud data utilizing a number of iterations of an Expectation-Maximum (EM) algorithm.

Abstract: In one embodiment, a system comprises: a global clock input for receiving a global clock, a plurality of partitions; and a skew tolerant interface configured to compensate for clock skew differences between a global clock from outside at least one of the partitions and a balanced local clock within at least one of the partitions. The partitions can be test partitions. The skew tolerant interface can cross a mesochronous boundary. In one exemplary implementation, the skew tolerant interface includes a deskew ring buffer on communication path of the at least one partition. pointers associated with the ring buffer can be free-running and depend only on clocks being pulsed when out of reset. The scheme can be fully synchronous and deterministic. The scheme can be modeled for the ATPG tools using simple pipeline flops. The depth of the pipeline can be dependent on the pointer difference for the read/write interface. The global clock input can be part of a scan link.

Abstract: A computer streaming system includes an application hints unit that provides an advisory hint for a remote user device corresponding to a selected streaming application, and a sending unit that manages streaming of the advisory hint and the selected streaming application over a network connected to the remote user device. Additionally, the computer streaming system includes a receiving unit that recovers the advisory hint for the remote user device, and a hints processing unit that applies the advisory hint to the remote user device when employing the selected computer application. Also, the computer streaming system includes a feedback unit that provides remote user feedback information over the network directed to responding to the advisory hint, and an update unit that provides the remote user feedback information. Also provided is a method of streaming a computer application.

Abstract: A method, computer readable medium, and system are disclosed for generating foveal images. The method includes the steps of redirecting first light rays towards an eye, where the first light rays are redirected by an optical combiner and produce a peripheral image and generating second light rays by a light engine. The second light rays are redirected towards the eye, where the second light rays intersect a first region of the optical combiner and converge at a nodal point within the eye and produce an inset foveal image positioned within at least a portion of the peripheral image. An origin of the second light rays is offset to intersect a second region of the optical combiner in response to a change in a gaze direction of the eye.

Abstract: In one embodiment, a test system comprises: a plurality of test partitions and a centralized controller configured to coordinate testing between the plurality of test partitions. At least one of the plurality of test partitions comprises: a partition test interface controller configured to control testing within at least one test partition in accordance with dynamic selection of a test mode, and at least one test chain configured to perform test operations. The dynamic selection of the test mode and control of testing within a test partition can be independent of selection of a test mode and control in others of the plurality of test partitions. In one embodiment, a free running clock signal is coupled to a test partition, and the partition test mode controller transforms the free running clock signal into a local partition test clock which is controlled in accordance with the dynamic selection of the test mode.

Abstract: A single-ended signal transmission system recovers a noise signal associated with a data input signal and uses the recovered noise signal to compensate for noise on the data input signal. The noise signal may be recovered from a noise reference signal line, or clock signal line, or a data signal line associated with a DC-balanced data input signal. The recovered noise signal may be represented as an analog signal or a digital signal. The recovered noise signal may be processed to compensate for DC offset and nonlinearities associated with one or more different input buffers. In one embodiment, the recovered noise signal includes frequency content substantially below a fundamental frequency for data transmission through the data input signal.

Abstract: A system including a series of partial product select encoders and partial product muxes, each of the partial product select encoders receiving a multiplier, receiving a carry input from a multiplier tree, and outputting a select signal to an associated partial product mux based on the multiplier and carry input, and each of the partial product muxes outputting a partial product based on the select signal and a multiplicand received.

Abstract: A clocked electronic device includes first and second control systems. The first control system is configured to decrease clock frequency in the device in response to decreasing supply voltage. The second control system is responsive to clock lag in the device and to an amount of current drawn through the device. It is configured to increase the supply voltage in response to increasing clock lag, but to decrease the supply voltage when the current drawn through the device exceeds an operational threshold.

Abstract: A method, computer readable medium, and system are disclosed for estimating optical flow between two images. A first pyramidal set of features is generated for a first image and a partial cost volume for a level of the first pyramidal set of features is computed, by a neural network, using features at the level of the first pyramidal set of features and warped features extracted from a second image, where the partial cost volume is computed across a limited range of pixels that is less than a full resolution of the first image, in pixels, at the level. The neural network processes the features and the partial cost volume to produce a refined optical flow estimate for the first image and the second image.

Abstract: A method and system for a DRAM having a first bank that includes a first sub-array (SA) and a second SA. The first SA includes a first storage unit coupled to a first row-buffer in a first sub-channel (FSC) and a second storage unit in a second sub-channel (SSC). The second SA includes a third storage unit and a fourth storage unit coupled to a second row-buffer. The first SA is associated with a first row address (RA) and the FSC is associated with a first column address (CA) stored in the FSC. The second SA is associated with a second RA and the SSC is associated with a second CA stored in the SSC. The first and second CAs are used to select portions of data from the first and second row-buffers, respectively, for output to a data bus.

Abstract: A method, computer readable medium, and system are disclosed for performing a texture level-of-detail approximation. The method includes the steps of identifying a scene to be rendered, projecting a ray passing through a pixel of a screen space, resulting in a first hit point at a geometry element within the scene, determining a footprint angle of the pixel, determining a curvature measure for the geometry element at the first hit point within the scene, computing a texture level of detail (LOD) approximation for a component of the scene, utilizing the footprint angle of the pixel and the curvature measure for the geometry element, and performing, utilizing a hardware processor, one or more rendering operations for the scene, utilizing the texture LOD approximation.

Abstract: A unified cache subsystem includes a data memory configured as both a shared memory and a local cache memory. The unified cache subsystem processes different types of memory transactions using different data pathways. To process memory transactions that target shared memory, the unified cache subsystem includes a direct pathway to the data memory. To process memory transactions that do not target shared memory, the unified cache subsystem includes a tag processing pipeline configured to identify cache hits and cache misses. When the tag processing pipeline identifies a cache hit for a given memory transaction, the transaction is rerouted to the direct pathway to data memory. When the tag processing pipeline identifies a cache miss for a given memory transaction, the transaction is pushed into a first-in first-out (FIFO) until miss data is returned from external memory. The tag processing pipeline is also configured to process texture-oriented memory transactions.

Abstract: The invention provides a method for adaptively adjusting a framerate of a graphic processing unit (GPU). For example, when the GPU workload is high and the temperature of the GPU is close to high temperature, the framerate can be decreased to reduce the workload; when the GPU workload is low, the framerate can be permitted to increase to raise the workload. By the present invention, the GPU is permitted to operate at maximum temperature. The method comprises the steps of: (a) receiving an execution parameter associated with at least one GPU; (b) comparing if the execution parameter is greater than a first reference value; and (c) in the event the execution parameter is greater than the first reference value, increasing a sleep time and power-gating the at least one GPU based on the sleep time to adjust the framerate.

Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to efficiently process requests to access memory that includes protected regions. Upon receiving an initial request via a virtual address (VA), the MMU translates the VA to a physical address (PA) based on page table entries (PTEs) and gates the response based on page-specific secure state information. To thwart software-based attempts to illicitly access the protected regions, the secure state information is not stored in page tables. However, to expedite subsequent requests, after the MMU identifies the PTE and the corresponding secure state information, the MMU stores both the PTE and the secure state information as a cache line in a translation lookaside buffer.