Abstract: It is described an RF communication device comprising: i) an RF antenna functionality; ii) at least one antenna pad connected to the RF antenna functionality; iii) a further functionality which is not an RF antenna functionality; and iv) at least one non-antenna pad electrically connected to the further functionality. The antenna pad and the non-antenna pad are arranged to be short-circuited with each other, and the non-antenna pad is electrically connected via a connection line to the further functionality within the RF communication device. Further, a method of manufacturing an RF communication device is described.

Abstract: A method of processing radar signalling, the method comprising: receiving a mask (815) that represents samples in the radar signalling that are detected as including interference. The mask (815) comprises a matrix of data having a first dimension and a second dimension, wherein the first dimension represents a fast-time axis and the second dimension represents a slow-time axis. The method further comprises performing frequency analysis on the mask (815) across each of the fast-time axis and the slow-time axis of the mask in order to provide a range-Doppler processed mask (817); and deconvolving a range-Doppler map (813) of the received radar signalling using the range-Doppler processed mask (817) in order to provide a deconvolved-range-Doppler map (814).

Abstract: An integrated circuit (IC) includes one or more active transistors and multiple series-coupled dummy transistors. The dummy transistors are coupled between two active transistors and/or at the ends of each active transistor. When the dummy transistors are coupled between two active transistors, apart from two conductive regions that are coupled to two active transistors, each remaining conductive region of the dummy transistors is maintained in a floating state to control a leakage current between the two active transistors. Similarly, when the dummy transistors are coupled at an end of one active transistor, apart from one conductive region that is coupled to the active transistor, each remaining conductive region of the dummy transistors is maintained in the floating state to control a leakage current between the active transistor and the dummy transistors.

Abstract: Aspects of the present disclosure are directed to communicating data for authentication and location determination, such as for authenticating a key FOB and locating the key FOB within a defined distance. As may be implemented in accordance with one or more embodiments, a plurality of headerless packets, respectively including scrambled timestamp sequence (STS) packets but not including encoding and/or synchronization headers, are communicated between respective communication circuits. A time of flight (TOF) value indicative of time elapsed between transmission and reception of the plurality of headerless packets is assessed based on the STS packets. A distance between the communication circuits is determined based on the assessed time of flight.

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

Abstract: A sequence recovery method is executed by a node in a time-sensitive network configured to transmit and receive packets The method includes providing a state variable, having a first state in which a packet loss counter is disabled, and a second state in which the packet loss counter is enabled. The packet loss counter can only be incremented to count lost packets when the loss state variable is in the second state. This method enhances the IEEE 802.1CB standard.

Abstract: An apparatus configured to receive an input dataset, x, indicative of radar signals reflected from targets as received at a plurality of antenna elements; define a matrix, A, formed of direction-of-arrival-angle vectors, an, each direction-of-arrival-angle vector representing an expected response at the plurality of antenna elements of radar signals from one of the targets; define a signal amplitude vector s to represent expected complex amplitudes as received in the radar signals; define an objective function based on x, A and s; search for a set of direction of arrival angles for each of the plurality of targets by the repeated evaluation of the objective function for a plurality of candidate matrices based on matrix A; and wherein said search space comprises a plurality of discrete points, z, associated with the direction of arrival angles by a function of sin(?k).

Abstract: A transceiver configured to: determine a reference frequency offset relative to a second transceiver based on double sided ranging; correct first and second portions of a packet received from a respective first and second antenna; and determine an angle of arrival of the packet based on corrected first and second portions and the reference frequency offset.

Abstract: The present disclosure relates to a MIMO radar system, comprising a first beamforming network (6) comprising a first beam ports (7A) and antenna ports (7B), wherein the first beamforming network is configured to connect the first beam ports via the first antenna ports to the first antenna elements, wherein the first beamforming network is configured to generate for each first beam port a single beam pattern. The first antenna elements transmitting or receiving a single beam pattern selected from the number of single beam patterns, wherein the first antenna elements are spaced apart at a first distance selected to provide a beam pattern of the first antenna array essentially consisting of a plurality of single main lobes. The radar system also has a similar second beamforming network (8).

Abstract: This disclosure relates to a network device comprising: a first input interface, a first output interface, and a second output interface, wherein the network device is configured to change from a first state, referred to as a time state, to a second state, referred to as a spatial state, and vice versa, wherein the network device is configured to generate each of a first output message and a second output message based on a first input message, wherein the network device is configured to transmit, in the time state, both, the first output message and the second output message, offset in time either via the first output interface or second output interface, and wherein the network device is configured to transmit, in the spatial state, the first output message via the first output interface and the second output message via the second output interface.

Abstract: Disclosed are methods and devices for, UWB, ranging of a target using a plurality of antenna arrays. The method comprises: determining a first RSSI, from a first antenna of a first antenna arrays, and a second RSSI from a second antenna of a second antenna arrays; in response to the first RSSI being larger than the second RSSI, selecting the first antenna array, and selecting the second antenna array otherwise; using the selected antenna array, performing a UWB ranging measurement including measuring an angle of arrival of the signal from the target; including, if the angle of arrival of the signal from the target is out of range: selecting a different one of the plurality of antennae arrays, as a presently-selected antenna array; and, using that antenna array, performing a UWB ranging measurement including measuring an angle of arrival of the signal from the target.

Abstract: A beamformer device for a multiple-input, multiple-output (MIMO) antenna system and method of operating a beamformer device is described. the beamformer device includes a number of beamformer channels. Each beamformer channel includes a RF terminal, an antenna connection terminal; and a power detector having a power detector output, The beamformer device includes a digital control interface comprising a serial data input and a serial data output; a control input coupled to the serial data input; and a beamformer monitor output configured to be selectively coupled to either the serial data output or the power detector output of one of the beamformer channels.

Abstract: A method of controlling a frequency-modulated oscillator 110 of a phase-locked loop circuit 100 is described, wherein the oscillator 110 comprises a bank of capacitors 413. The method comprises the steps of (i) switching a capacitor 414 of the bank of capacitors 413 to change an output frequency 1050 of an output signal 112 of the oscillator 110 from a first frequency 1051 to a second frequency 1052, (ii) determining a frequency information associated with the capacitor 414 and based on at least one of the first frequency 1051 and the second frequency 1052; and (iii) writing the frequency information to a look-up table 224, 225, 226 stored in a control unit 120 of the oscillator 110. A corresponding frequency-modulated oscillator 110 and phase-locked loop circuit 100 are also described.

Abstract: One example discloses a power on reset (POR) circuit, wherein a first circuit is configured to un-couple a power supply input from a resistor divider when the voltage on a second end of the capacitor is above a first circuit threshold; a second circuit configured to couple the second end of the capacitor to the power supply input when a voltage on at least one tap point of the resistor divider is above a second circuit threshold; wherein the comparator is coupled to at least one of the tap points, the reference potential, and a POR output; and wherein the comparator is configured to ramp-up a POR signal on the POR output when a voltage on the at least one of the tap points is greater than the comparator threshold.

Abstract: A method is provided for detecting a profiling attack in an electronic device. The method includes causing provisioning of the device with a key and causing key operations using the key. A total key provisions counter value of a total key provisions counter is updated in response to the key provisioning. Also, a counter value of a total operations counter corresponding to a total number of operations is updated using the detected provisioned keys. A predetermined relationship between the total key provisions counter value and the total operations counter value is detected. An indication of the profiling attack is provided in response to the relationship meeting a predetermined criterion. In another embodiment, an electronic device having a total key provisions counter value and a total key operations counter value is provided. A predetermined relationship between the counter values indicates a profiling attack of the electronic device.

Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a communication unit configured to execute a time-of-flight ranging session with an external communication counterpart; a clock offset measurement unit configured to measure a frequency offset of a device clock, wherein said device clock is configured to be used by the communication unit when said ranging session is executed; a processing unit configured to determine whether the measured frequency offset of the device clock has a predefined correlation with a frequency offset of a counterpart clock, wherein said counterpart clock is configured to be used by the external communication counterpart when said ranging session is executed. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: One example securely updates an integrated circuit to mitigate undesirable modifications and this involves an application circuit accessing an external network while a (e.g., nonvolatile) program memory is write protected; and a reset-boot circuit resetting and booting the application circuit while access to the external network is disabled, and causing an update for the application circuit. In response to an indication that an update is downloaded for installation, the downloaded update is installed in the memory while access to the external network is disabled, and execution of the reset mode is permitted after the update is installed. Also, a retrieval module may download, in response to an indication that an update is not downloaded, an update provided via the external network while the memory is write-protected and thereby permitting execution of the reset mode after the update is downloaded.

Abstract: Systems and methods for detection of persistent faults in processing units and memory have been described. In an illustrative, non-limiting embodiment, a Machine Learning (ML) processor includes one or more registers, and a data moving circuit coupled to the one or more registers. The data moving circuit can be configured to select, based upon a first value stored in the one or more registers, an original one of a plurality of parallel handling circuits within the ML processor to obtain an original data processing result. The data moving circuit can also be configured to select, based upon a second value stored in the one or more registers, an alternative one of the plurality of parallel handling circuits to obtain an alternative data processing result that, upon comparison with the original data processing result, provides an indication of a persistent fault in the ML processor.

Abstract: A network station scheduling a frame to be transmitted by a transmitter of the network station at a transmit time. The transmit time is based on a first clock. A request is then issued to a direct memory access (DMA) circuit to retrieve the frame from a system memory. An advance time offset associated with the first clock is determined based on an estimated DMA latency of the DMA circuit. A frame retrieved by the DMA circuit is provided to a staging circuit. When a time of a second clock reaches the transmit time of the frame in the staging circuit, the frame is transmitted at the transmit time. In an example, a time of the first clock is ahead of a time of the second clock by the advance time offset.

Abstract: A system-on-chip (SoC) method and apparatus are disclosed for checking end-to-end integrity of communications over an network interconnect, where the SoC includes an initiator subsystem connected over the network interconnect to a target subsystem, wherein a first integrity module is configured to compute a first integrity value based on regular transaction messages sent or received by the initiator subsystem and to send a protecting information transaction (PIT) message over the network interconnect to the target subsystem, wherein a second integrity module is configured to compute a second integrity value based on regular transaction messages sent or received by the destination subsystem and to send a PIT response message over the network interconnect to the initiator subsystem, and wherein a compatibility module compares the first and second integrity values to verify the end-to-end integrity of the regular transaction messages sent or received over the network interconnect.