Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: at least two antennas; an ultra-wideband (UWB) communication unit configured to receive UWB frames through said antennas; a controller configured to switch between said antennas such that consecutive UWB frames are received through different ones of said antennas; wherein the controller is further configured to compute channel impulse responses (CIRs) wherein each of said CIRs is based on a different one of said UWB frames. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.

Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.

Abstract: Various embodiments relate to a hardware device configured to compute a plurality of chained hash functions in parallel, including: a processor implementing p hash functions configured to operate on a small input, where p is an integer; a data unit connected to the plurality of hash functions, configured to store the outputs of plurality of hash functions that are then used as the input to a next round of computing the hash function, wherein the processor receives a single instruction and p small data inputs, and wherein each of the p hash functions are used to perform a chained hash function operation on a respective small input of the p small inputs.

Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.

Abstract: A wireless communication system (100) estimates a carrier frequency offset between wireless devices (101, 102) by configuring the devices through exchanging packet configuration packets (121, 125) to specify a carrier frequency offset fingerprint (CFOF) sequence in a measurement packet (133, 136) which is transmitted between the wireless devices, where the CFOF sequence in the measurement packet includes a prefix component (31), one or more signature segments (32), and a suffix component (33) for performing CFO measurements at the wireless devices which each process IQ samples corresponding to the signature segments in the received measurement packet by correlating the IQ samples against a reference vector to generate, for each of the one or more signature segments, a carrier frequency offset estimate between the first and second wireless devices.

Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.

Abstract: A double IO pad cell including a busing frame formed on a busing metal layer aligned with a same-sized component frame integrated on a component layer of an IC. The busing frame includes first and second IO pads, a supply voltage rail, and a ground voltage rail. The component frame includes first and second primary ESD circuitry each including a first diode coupled between a respective one of the first and second IO pads and the supply voltage rail and a second diode coupled between the respective IO pad and the ground voltage rail. The second diodes of each primary ESD circuitry are integrated adjacent each other sandwiched between the first diodes which act as collector guard bands for the second diodes. The diodes of each primary ESD circuitry of the component frame are aligned with a corresponding one of the first and second IO pads of the busing frame.

Abstract: A method for detecting a fault injection is described. The method includes providing a secondary code, the secondary code including a predetermined function with a known expected result when the secondary code is executed with a known tested input. A primary code is executed in the data processing system. The primary code may be a portion of code that requires protection from a fault injection attack, such as for example, security sensitive code. The secondary code is executed in parallel with the primary code execution in the data processing system to produce an output. The output is compared with the known expected result to detect the fault injection attack of the data processing system. In one embodiment, the secondary code is not related to the primary code.

Abstract: A controller for a DC-DC converter that includes an inductor. The DC-DC converter has three phases of operation: a first phase, in which an input voltage charges the inductor; a second phase, in which the inductor discharges to a load; and a third phase, in which the inductor is disconnected from the load and in which the input voltage does not charge the inductor. The controller is configured to set a control-factor based on the input voltage of the DC-DC converter, and set the duration of the third phase based on the control-factor and the sum of the duration of the first phase and the second phase.

Abstract: A method is provided for protecting a machine learning model from a side channel attack. A weighted sum vector having first and second elements is initialized. A weight vector for a connection between a node of a first layer and a node of a second layer is multiplied with an input vector to the node of the first layer. A first element of the weight vector includes a weight, and a first element of the input vector includes the input. A second element of the weight vector is a negation of the first element of the weight vector and the second element of the input vector equals the first element of the input vector. A multiplication result is added to the weighted sum vector to produce a computed weighted sum vector. An output vector including the computed weighted sum vector is provided to the node of the second layer.

Abstract: A communication device and method are provided for communicating data, such as a cryptographic key, wirelessly to another communication device. The communication device and the other device each include an oscillator circuit portion, an inverter, a non-inverting buffer, and a switch for switching between the inverter and non-inverting buffer. A circular loop is formed wirelessly between the oscillator circuit portions of both devices by placing both communication devices near each other. A control circuit in each device measures a parameter such as frequency or waveform pattern of the circulating signal to determine how to position the switches. The oscillator circuit portions may be portions of the same oscillator distributed between the devices, such as a delay line-controlled oscillator or a chaotic oscillator. Inverting and not inverting the circulated signal changes the parameter of the signal so that it is difficult for an eavesdropper to learn the communication.

Abstract: A CAN module that can be integrated between a CAN controller and a CAN transceiver includes a receive data (RXD), input interface for receiving a first bit sequence through a RXD stream and a RXD output interface for sending a manipulated receive data (MRXD), stream including a second bit sequence. A processing logic of the CAN module is configured to manipulate the first bit sequence to generate a second bit sequence comprising a second stuff bit at a second position in the second bit sequence corresponding to a first position of a first stuff bit in the first bit sequence such that the second stuff bit is complementary to a preceding bit of the second stuff bit in the second bit sequence. The present disclosure also relates to a method for the CAN module.

Abstract: Various implementations relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including a masked decomposition of a polynomial a having ns arithmetic shares into a high part a1 and a low part a0 for lattice-based cryptography in a processor, the instructions, including: performing a rounded Euclidian division of the polynomial a by a base ? to compute t(?)A; extracting Boolean shares a1(?)B from n low bits of t by performing an arithmetic share to Boolean share (A2B) conversion on t(?)A and performing an AND with ??1, where ?=???1 is a power of 2; unmasking a1 by combining Boolean shares of a1(?)B; calculating arithmetic shares a0(?)A of the low part a0; and performing a cryptographic function using a1 and a0(?)A.

Abstract: A data processing system has a processor and a system memory. The system memory may be a dynamic random-access memory (DRAM). The processor includes an embedded memory. The system memory is coupled to the processor and is organized in a plurality of pages. A portion of the code or data stored in the plurality of memory pages is selected for permutation. A permutation order is generated and the memory pages containing the portion of code or data is permuted using a permutation order. The permutation order and/or a reverse permutation order to recover the original order may be stored in the embedded memory. Permuting the memory pages with a permutation order stored in the embedded memory prevents the code or data from being read during a freeze attack on the system memory in a way that is useful to an attacker.

Abstract: A method is provided for partitioning a plurality of devices in a communications system. The method includes providing the communications system with a central server that communicates with each of the plurality of devices. The communications system communicates in a plurality of time periods. The plurality of devices is partitioned into two or more groups of devices. Time periods of the plurality of time periods are assigned for communications of the two or more groups of devices. Time intervals between the time periods for the two or more groups are determined to be co-prime time intervals greater than one, and each of the two or more groups is assigned a different time interval of the co-prime time intervals. The two or more groups are active for communications only during the assigned time periods determined by the co-prime time intervals. A device is also provided for operating in the communications system.

Abstract: Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

Abstract: Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

Abstract: It is described a method, a control device, and a computer program for enabling/disabling at least one near field communication (NFC) function of a mobile device (MD). It is further described such a MD. The method comprises (a) associating the at least one NFC function to be enabled/disabled with a corresponding secure application (SA) installed in a secure element (SE) system; (b) checking whether the SA complies with a predefined secure condition; (c) if the SA complies with the predefined secure condition, transmitting a notification from the SA to the NFC control system (NFCC) via an interface between the SE system and the NFCC; and (d) enabling/disabling, by the NFCC, the at least one NFC function based on information comprised by the transmitted notification.

Abstract: Various embodiments relate to a system for provisioning a cryptographic device, including: a memory; a processor coupled to the memory, wherein the processor is further configured to: determine a maximum PQC private key size, maximum PQC public key size, and maximum PQC updater size of a plurality of post quantum cryptography algorithms; provision memory in the cryptographic device to store a PQC-update non-PQC private key, a secret PQC-update non-PQC public key, PQC private key, PQC public key, and PQC updater based upon the determined maximum PQC private key size, maximum PQC public key size, and maximum updater size; and provision the cryptographic device with the PQC-update non-PQC private key, the secret PQC-update non-PQC public key, a non-PQC secret key, a non-PQC public key, and non-PQC algorithm code configured to carry out non-PQC cryptographic algorithms.

Abstract: A radar processor for processing a frame of radar data received from one or more targets, the frame of radar data having a carrier frequency and comprising a sequence of codewords with a codeword repetition interval, wherein the carrier frequency and the codeword repetition interval define an unambiguous velocity range, the radar processor configured to: receive the frame of radar data; transform the frame to obtain a velocity data array; apply a correction algorithm to the velocity data array to correct a Doppler shift of the frame to obtain a corrected array, wherein the correction algorithm comprises a set of Doppler correction frequencies corresponding to a set of velocity gates and at least one of the set of Doppler correction frequencies corresponds to a velocity gate outside the unambiguous velocity range; and perform range processing on the corrected array to obtain a range-Doppler map.