Patents Assigned to NXP B.V.
  • Publication number: 20240168907
    Abstract: Aspects of the subject disclosure may include, for example, remapping a first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines, the first remapped address bus supplying updated address information, connecting the first address remapped bus to an address translation unit (ATU), the ATU configured to translate the updated address information into translated address information supplied to a second address bus, and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the second remapped address bus changing the translated address information into updated translated address information.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 23, 2024
    Applicant: NXP B.V.
    Inventor: Benjamin Charles Eckermann
  • Patent number: 11990664
    Abstract: A transmission line. The transmission line includes a reference electrode. The transmission line also includes a stripline. The stripline meanders within a plane. The stripline has a non-planar profile when viewed along a direction parallel to the plane.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: May 21, 2024
    Assignee: NXP B.V.
    Inventors: Mustafa Acar, Philipp Franz Freidl, Dominicus Martinus Wilhelmus Leenaerts
  • Patent number: 11990536
    Abstract: A semiconductor device and fabrication method are described for manufacturing a heterojunction bipolar transistor by forming a silicon collector region in a substrate which includes a lower collector layer, a dopant diffusion barrier layer, and an upper collector layer, where the formation of the dopant diffusion barrier layer reduces diffusion of dopants from the lower collector layer into the upper collector layer during one or more subsequent manufacturing steps which are used to form a trench isolation region in the substrate along with a heterogeneous base region and a silicon emitter region.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: May 21, 2024
    Assignee: NXP B.V.
    Inventors: Johannes Josephus Theodorus Marinus Donkers, Petrus Hubertus Cornelis Magnee, Ronald Willem Arnoud Werkman
  • Patent number: 11985217
    Abstract: An apparatus for providing an interface between a first network that operates based on a first protocol and a second network that operates based on a second protocol, includes a receive terminal configured to receive one or more first messages encoded according to the first protocol, the first messages encapsulating a plurality of second messages. The apparatus is configured to extract encapsulated second messages, determine for each of extracted second messages, and based on flow identifying information of each of extracted second messages, a flow to which the extracted second message belongs. The extracted second messages of the flow provide for transmission of the extracted second messages on the second network encoded based on the second protocol with a time spacing there between greater than a predetermined minimum time spacing.
    Type: Grant
    Filed: January 27, 2023
    Date of Patent: May 14, 2024
    Assignee: NXP B.V.
    Inventor: Christian Herber
  • Patent number: 11984904
    Abstract: An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC) and a comparator having a first input coupled to receive an output voltage of the DAC, a second input, and a comparison output. The ADC also includes successive-approximation-register (SAR) circuitry having an input to receive the comparison output, and an output to provide an uncalibrated digital value. The DAC includes a Most Significant Bits (MSBs) sub-DAC including a set of MSB DAC elements and a Least Significant Bits (LSBs) sub-DAC including a set of LSB DAC elements. The ADC also includes calibration circuitry which receives the uncalibrated digital value and applies one or more calibration values to the uncalibrated digital value to obtain a calibrated digital value. The calibration circuitry obtains a calibration value for each MSB DAC element using the set of LSB DAC elements, the termination element, and at least one of the one or more redundant DAC elements.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: May 14, 2024
    Assignee: NXP B.V.
    Inventor: Michael Todd Berens
  • Patent number: 11977181
    Abstract: An apparatus, such as a radar system that conducts beamforming operations, includes a plurality of analog-to-digital-converters (ADCs) and an error correction system coupled to the ADCs. Based upon an assessment of a plurality of errors associated with the ADCs by the error correction system, the error correction system programs sampling operations for the ADCs. The error correction system includes an error correction unit that identifies the plurality of errors associated with a plurality of sub-ADCs of the ADCs, a selection unit coupled to the error correction unit that sorts the errors associated with the plurality of sub-ADCs, and a programming unit coupled to the selection unit that reconfigures the sorted errors to generate a sequence of sampling operations for the plurality of sub-ADCs.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: May 7, 2024
    Assignee: NXP B.V.
    Inventors: Pavlos Athanasiadis, Konstantinos Doris, Marios Neofytou, Georgi Ivanov Radulov
  • Patent number: 11979157
    Abstract: It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising: i) a multiplier device (110), configured to receive a single-ended incoming signal (105), and multiply the incoming signal (105) to provide a multiplied signal (115); and ii) a divider device (120), configured to receive the multiplied signal (115), and divide the multiplied signal (115) to provide a differential signal (125a, 125b). Further, a corresponding signal conversion method is described.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: May 7, 2024
    Assignee: NXP B.V.
    Inventors: Stefano Dal Toso, Olivier Susplugas
  • Patent number: 11971445
    Abstract: The disclosure relates to an integrated circuit and associated method and packaged integrated circuit. The integrated circuit comprises a first pad; a second pad; an active element having a node that is capacitively coupled to the first and second pads; a voltage or current source connected to the first pad; and a detection module connected to the second pad and configured to determine an electrical continuity between the second pad and the first pad.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 30, 2024
    Assignee: NXP B.V.
    Inventor: Anton Salfelner
  • Patent number: 11973551
    Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: a plurality of antennas; a communication unit configured to execute ranging sessions with an external communication counterpart through said antennas; an antenna selection unit configured to select a specific antenna from said plurality antennas for carrying out one or more of said ranging sessions, wherein the antenna selection unit is configured to select said specific antenna in dependence on one or more parameters indicative of a communication quality between the antennas and the external communication counterpart. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: April 30, 2024
    Assignee: NXP B.V.
    Inventors: Dorian Haslinger, Wolfgang Eber, David Veit
  • Patent number: 11971740
    Abstract: An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: NXP B.V.
    Inventors: Roel Lieve P Uytterhoeven, Wim Dehaene
  • Patent number: 11965847
    Abstract: A method and apparatus are described for a reconfigurable architecture analog front end architecture for electrochemical sensors. In one example, an analog front end includes an electrode driver stage coupled to electrodes of an electrochemical sensor, and measurement channels coupled to the electrode driver stage to receive an electrode signal from the electrodes of the electrochemical sensor and to generate measurement results, the measurement channels configured to switch configurations to perform different measurements.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: April 23, 2024
    Assignee: NXP B.V.
    Inventors: Costantino Ligouras, Sergio Andrés Rueda Gómez, Harry Neuteboom, Muhammad Kamran, Dave Sebastiaan Kroekenstoel, Rinze Ida Mechtildis Peter Meijer
  • Patent number: 11967967
    Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 23, 2024
    Assignee: NXP B.V.
    Inventors: Qilong Liu, Shagun Bajoria, Lucien Johannes Breems
  • Patent number: 11961314
    Abstract: A method is described for analyzing an output of an object detector for a selected object of interest in an image. The object of interest in a first image is selected. A user of the object detector draws a bounding box around the object of interest. A first inference operation is run on the first image using the object detector, and in response, the object detect provides a plurality of proposals. A non-max suppression (NMS) algorithm is run on the plurality of proposals, including the proposal having the object of interest. A classifier and bounding box regressor are run on each proposal of the plurality of proposals and results are outputted. The outputted results are then analyzed. The method can provide insight into why an object detector returns the results that it does.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventors: Gerardus Antonius Franciscus Derks, Wilhelmus Petrus Adrianus Johannus Michiels, Brian Ermans, Frederik Dirk Schalij
  • Patent number: 11960358
    Abstract: Various embodiments relate to a memory controller configured to read data from a memory array, including: an error correction codes (ECC) encoder configured to encode data stored in the memory array; an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and a fault controller configured to: command the memory controller to read other data from the memory array when the ECC detects an error; command the memory controller to re-read the first data from the memory array; when the ECC detects an error; compare the re-read first data to the read first data; and signal a fault attack when the re-read first data is different from the read first data.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventor: Björn Fay
  • Patent number: 11962331
    Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventor: Robert van Veldhoven
  • Patent number: 11963291
    Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventors: Leo van Gemert, Michael B. Vincent
  • Patent number: 11962305
    Abstract: A true random number generator circuit includes a ring oscillator and a plurality of sampling circuits. The ring oscillator includes a plurality of series-connected stages coupled together in a ring. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. A sampling circuit of the plurality of sampling circuits has an input coupled to a node located between two adjacent stages of the plurality of series-connected stages. Every node of the ring oscillator is coupled to a corresponding sampling circuit of the plurality of sampling circuits. In another embodiment, a method for generating a random number is provided.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: April 16, 2024
    Assignee: NXP B.V.
    Inventor: Björn Fay
  • Patent number: 11955729
    Abstract: Embodiments of an antenna system and a method for operating an antenna are disclosed. In an embodiment, an antenna system includes a first ferrite element, a second ferrite element, a first coil wrapped around the first ferrite element, a second coil wrapped around the second ferrite element, a first antenna interface electrically coupled to the first coil, a second antenna interface electrically coupled to the second coil, and a conductor network connected between the first coil, the second coil, the first antenna interface, and the second antenna interface.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: April 9, 2024
    Assignee: NXP B.V.
    Inventors: Oliver Kronschläger, David Knabl, Andreas Merl, Michael Stark, Erich Merlin
  • Publication number: 20240111624
    Abstract: Various embodiments relate to a memory controller configured to read data from a memory array, including: an error correction codes (ECC) encoder configured to encode data stored in the memory array; an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and a fault controller configured to: command the memory controller to read other data from the memory array when the ECC detects an error; command the memory controller to re-read the first data from the memory array; when the ECC detects an error; compare the re-read first data to the read first data; and signal a fault attack when the re-read first data is different from the read first data.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: NXP B.V.
    Inventor: Björn FAY
  • Patent number: 11947672
    Abstract: A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: April 2, 2024
    Assignee: NXP B.V.
    Inventors: Andreas Bernardus Maria Jansman, Andreas Lentz