Abstract: An electrochemical sensor measurement unit is described including a sensor degradation signature unit and a processing unit coupled to the sensor degradation signature unit. The processing unit includes a processor first input configured to be coupled to a sensor output of an electrochemical sensor and a processor first output configured to be coupled to a sensor input of an electrochemical sensor. The processing unit is configured to apply a stimulus signal to the sensor input; receive an electrochemical sensor signal via the sensor output. The processing unit may then determine at least one sensor parameter at one or more time values from the received sensor signal. The processing unit determines a predicted lifetime value corresponding to an expected remaining lifetime of the electrochemical sensor dependent on the sensor degradation signature and the at least one sensor parameter.

Abstract: A method is provided for detecting non-problem domain (NPD) data in a machine learning (ML) model. The method includes training the ML model using problem domain (PD) training data. A second fully connected layer is added to the trained ML model in parallel with a first fully connected layer in the trained ML model. The trained ML model is retrained with NPD training data while preventing weights in the ML model from changing except for weights of the second fully connected layer. An inference operation is performed with the retrained ML model. Output vectors are received from the first and second fully connected layers via a Softmax layer. A metric is computed using the output vectors. The metric is compared to a threshold metric to determine if input samples are PD or NPD. An indication is provided when NPD data is detected. In another embodiment, a ML model is provided.

Abstract: In one example, the present disclosure includes a circuit-based apparatus including a resonance tank circuit, a signal source, and a single-ended circuit. The signal source provides a plurality of complementary signals (e.g., differential signals) for processing by the resonance tank circuit where the complementary signals are combined to a signal at a node for presentation to the single-ended circuit (e.g., antenna or receiver). For example, the resonance tank circuit, which has a resonance frequency set for a transfer of power to the load and which may be impedance matched to the single-ended circuit, converts the complementary signals to the node for carrying the signal to the single-ended circuit.

Abstract: A circuit includes a secure chip storing one of an enclave of key values linked to an update code; a memory to store an updatable data set including an update value, which corresponds to and is revised with the update code; and a logic circuit. The logic circuit is configured to provide a key value based on a revision to the update code from the enclave of key values, generate an authentication tag as a function of the key value, use the authentication tag to verify that the updatable data set is valid and current before using the updatable data set in an application, and update the data set by storing a replacement updatable data set including a revised update value in the memory circuit. The revised update value corresponds to a revised update code to provide another key value from the enclave of key values.

Abstract: In accordance with a first aspect of the present disclosure, a tunable attenuator is provided, comprising: one or more transformer windings configured to facilitate attenuating a signal; one or more conductive loops provided underneath the transforming windings; a controller configured to control an amount of current flowing through the conductive loops, thereby providing a tunable attenuation of said signal. In accordance with a second aspect of the present disclosure, a corresponding method of producing a tunable attenuator is conceived.

Abstract: In accordance with a first aspect of the present disclosure, a networkable lighting device is provided, comprising: an ultra-wideband (UWB) communication unit; a mode controller operatively coupled to the UWB communication unit; wherein the mode controller is configured to cause the UWB communication unit to operate in a radar mode; and wherein the UWB communication unit is configured to, when operating in said radar mode, detect at least one living object present within a predefined area around or near the lighting device. In accordance with a second aspect of the present disclosure, a corresponding method of operating a networkable lighting device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.

Abstract: A data processing system is provided that includes a memory, a processor, and a memory integrity circuit. The memory includes a plurality of memory regions configured to store information. The processor is configured to execute instructions to access an address in the memory. The memory integrity circuit is coupled to the processor and to the memory, and configured to validate read and write accesses to the memory by the processor. The memory integrity circuit validates a write access to an address of a memory region of the plurality of memory regions in response to n number of the read accesses being validated prior to the write access, where n is an integer, and in response to correctly calculating a message authentication code (MAC) of a combination of encrypted data stored at the address and a tweak value. In another embodiment, a method is provided for isolation security for the memory.

Abstract: An integrated circuit includes a secure asset, a security system, and an efficacy decoder. The security system is triggered to operate in one of its functional states. Further, the security system receives various test requests for an access to the secure asset, and determines, based on the triggered functional state thereof, one or more test requests authorized to access the secure asset. The efficacy decoder similarly receives the test requests and determines one or more allowable requests for the triggered functional state of the security system. Further, the efficacy decoder determines an efficacy value for the security system based on a comparison between the test requests authorized by the security system and the allowable requests associated with the triggered functional state. The efficacy value is indicative of a security level of the security system operating in the triggered functional state.

Abstract: The present disclosure relates to a voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator including a voltage supply terminal for receiving a supply voltage; an output terminal for outputting the regulated output voltage; a reference terminal; a feedforward Wilson current mirror; and a flipped voltage follower, FVF.

Abstract: A device such as a key fob includes a wireless interface for establishing a wireless connection to a controller integrated in a vehicle. The key fob is configured provide access credentials to the controller via the wireless connection. The key fob also includes a wired interface for connecting the key fob to a console integrated in the vehicle. When connected to the console, the key fob can be used to wirelessly charge an external mobile device. In addition, or in the alternative, the key fob can be used as an anchor device for performing ranging operations with an external mobile device.

Abstract: An RF device includes a first channel with a first frequency band, configured to receive a first signal; and a second channel with a second frequency band, configured to receive a second signal. The first frequency band and the second frequency band are different. The device includes control circuitry configured to obtain a first channel response associated with the received first signal at the first channel, to obtain a second channel response associated with the received second signal at the second channel and to calibrate the first channel response and the second channel response by steering to a calibration base. The control circuitry is further configured to calibrate the first channel response and second channel response by channel stitching to obtain a combined channel response.

Abstract: A method includes generating a plurality of chirps to be transmitted in a radar frame of a radar signal. Each chirp of the plurality of chirps has a corresponding chirp slope, and chirp slopes of a first subset of the plurality of chirps monotonically vary from a first chirp of the first subset to a last chirp of the first subset. The method also includes transmitting the plurality of chirps during a radar frame in a radar signal. After receiving the reflection of the radar signal, the method includes processing the received radar signal based on parameters associated with the generated plurality of chirps with the different chirp slopes.

Abstract: A power-on reset (POR) circuit includes a first transistor and a stack of transistors. The first transistor generates an enable voltage based on a first supply voltage. The enable voltage is a reduced version of the first supply voltage and ramps up based on a ramp-up of the first supply voltage. The stack of transistors generates a control voltage. The control voltage is a reduced version of the enable voltage and ramps up based on the ramp-up of the enable voltage. The control voltage delays ramping of the enable voltage such that the enable voltage ramps up to a first threshold voltage associated with the stack of transistors in a first time period. Further, a reset signal generated by the POR circuit is asserted when the enable voltage exceeds the first threshold voltage at the end of the first time period.

Abstract: Embodiments of a multiphase clock generation device may include an input for feeding a reference clock, a clock generation unit adapted to generate phase-shifted clock signals from the reference clock, and a phase comparator unit functionally coupled with the clock generation unit. The phase comparator unit is adapted to measure a phase shift of the phase-shifted clock signals. The multiphase clock generation device includes a self-calibration unit that is functionally coupled with the clock generation unit. The calibration unit outputs a delay-calibration parameter to the clock generation unit. The clock generation unit is adapted to generate a multiphase clock signal out of the reference clock and the delay-calibration parameter.

Abstract: Systems and methods for delta-sigma modulators with downsampled digital integrators. In various embodiments, a delta-sigma modulator may include: a comparator configured to receive an analog input and to provide a digital output at a sampling frequency, where the digital output is applied to an integrator path and to a feed-forward path; a digital integrator in the integrator path, where the digital integrator is configured to operate with a clock frequency that is less the sampling frequency; and a summer configured to add an output of the integrator path to an output of the feed-forward path to produce a bitstream.

Abstract: A data processing system and a method are provided for executing an obfuscated computer program. A function that computes an obfuscated address for each instruction of a plurality of instructions is provided. The function is factored into a first part and a second part. The first part is stored in a memory of the data processing system. The second part and a secret are stored in a secure element of the data processing system, where the secure element is relatively more secure than the memory. An instruction of the plurality of instructions is received in the data processing system. A processor of the data processing system computes an intermediate obfuscated address using the first part. The intermediate obfuscated address is provided to the secure element. An unobfuscated address is computed in the secure element using the intermediate obfuscated address, the second part, and the secret.

Abstract: A method is provided for cooperative malfunction detection between an observer vehicle and an observed vehicle. The method includes requesting, by the observed vehicle, a report of observed malfunctions of the observed vehicle from the observer vehicle via a vehicle-to-vehicle (V2V) communication system. The observer vehicle detects and captures sensor data of the observed vehicle by the observer vehicle. Then, in one embodiment, the observer vehicle transmits the captured sensor data to the observed vehicle using the V2V communication system. The observed vehicle runs a malfunction detection function on the captured sensor data and generates a report summarizing the malfunction. Alternatively, the observer vehicle generates the report and transmits it to the observed vehicle. The driver of the observed vehicle is notified of the report. In another embodiment, a data processing system is provided for performing the method in the observer vehicle or the observed vehicle.

Abstract: A system and method are presented. A plurality of target objects are determined by a radar system. Each target object in the plurality of target objects is associated with a distance value and a velocity value. A power reduction factor is determined using the distance value and the velocity value associated with each target object of the plurality of target objects. A second radar signal is transmitted at a second power level determined by the power reduction factor.

Abstract: An integrated circuit (IC), including a clocking system, a plurality of clock gate controllers, and a plurality of clock gates, is provided. During a capture phase of an at-speed testing of the IC, the clocking system generates an at-speed clock signal including launch and capture pulses that are extracted from a reference clock signal based on a capture phase frequency. The plurality of clock gate controllers generates a plurality of enable signals such that for the launch pulse, one enable signal is asserted, and for the capture pulse, the same or different enable signal is asserted. Each of the plurality of clock gates is activated based on an assertion of a corresponding enable signal. Further, during the capture phase, one or more activated clock gates enable the at-speed testing of the IC based on the at-speed clock signal.

Abstract: A data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for generating keys in a hash based signature system in a processor, the instructions, including: generating, by a random number generator, a seed; repeatedly hashing the seed with a first hash function to produce n/k chained seeds, wherein n is a total number secret keys generated and k is a number of secret keys generated from each chained seed; and generating k secret keys from each of the n/k chained seeds using a second hash function, wherein at least one of the k secret keys is generated from another of the k secret keys in a sequential chain.