Abstract: A transceiver for sending and receiving data from a controller area network (CAN) bus is disclosed. The transceiver includes a microcontroller port, a transmitter and a receiver, wherein the transceiver is configured to determine bit timings from a data frame received by the receiver. The transceiver is further configured to detect attempts to introduce a signal glitch in a predetermined portion of the data frame and upon detection of the signal glitch, the transceiver is configured to invalidate the data frame on a transmission line and/or disable the transmitter for a predetermined period.

Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.

Abstract: Described are method and systems that implement time frequency domain threshold interference and localization fusion to resolve interference issues in an automotive radar system, that produces spectrograms using Short-Time Fourier Transform (STFT) for all receiving antennas of the automotive radar system. For each STFT frequency a suppression threshold is determined. Interference is isolated for each STFT frequency by removing the interference from samples that are above the suppression threshold by using a filter. Direction of Arrival (DoA) is estimated for each interference spectrogram cell using measurements from all the receiving antennas. Interference samples are clustered using the DoA into epochs of chirps.

Abstract: A digital signal generator apparatus and method is described. The digital signal generator includes a counter, an integrator and a comparator. The counter counts up or down from an initial counter value dependent on a counter control input. The comparator has a first input coupled to the counter output, a threshold input and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to the digital signal generator output. The digital signal generator determines the count direction after the initial direction dependent on the comparison between a threshold value applied to the threshold input and the counter output value. The digital signal generator may implement the generation of a waveform having an approximation to a raised cosine function. The generated waveform may be used for audio artefact reduction in an audio amplifier during mute or unmute operations or during power up power down operations.

Abstract: A technique for handling an integrated circuit tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit tape assembly on a film frame carrier (FFC) frame, stretching the dicing tape while on the FFC frame, and securing the stretched dicing tape by engaging a spring ring with the dicing tape and FFC frame. Adjacent integrated circuits are thereby inhibited from colliding during shipment or storage for subsequent processing.

Abstract: A fractional-N all digital phase locked loop (ADPLL) includes a randomly modulated delay having a triangular distribution to a frequency reference at an input of the fractional-n ADPLL to reduce spurious tones introduced by delta-sigma modulation of a frequency control word without requiring active control or calibration. In some embodiments, a delay line generates the randomly modulated delay based on a uniformly distributed random number with a flat spectrum that is shaped by a high pass filter.

Abstract: A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

Abstract: Various example embodiments are directed to apparatuses and methods including an apparatus having sensor circuitry and processing circuitry. In one example, sensor circuitry produces and senses detected signals corresponding to physical objects located in an operational region relative to a location of the sensor circuitry. The processing circuitry records and organizes information associated with the detected signals in a plurality of sub-histograms respectively associated with different accuracy metrics for corresponding sub-regions of the operational region, each of the plurality of sub-histograms including a set of histogram bins characterized by a bin width linked to its accuracy metric, and refines at least one of the accuracy metric by adapting one or more of the bin widths dynamically in response to the detected signals.

Abstract: Aspects of the present disclosure are directed to ascertaining whether data messages are repetitions of a previous data message. As may be implemented in accordance with one or more embodiments characterized herein, data packets (130/131) are received (102) and which use a first time delay relative to transmission of a previous data packet (120/121) by a different transmitter. Repetitions (110A/111A) of data packets are also received (102), and which use a second time delay relative to transmission of a previous data packet (110/111) by the same transmitter. The second time delay is less than the first time delay. The received packet is identified (102) as being a repetition of an immediately-previous data packet based on a time delay between the data packet and the immediately-previous data packet, relative to the first and second time delays.

Abstract: A method for managing an anonymous e-cash transaction includes receiving a request to withdraw a payment coin, generating a combination of random attributes for the payment coin, creating the payment coin based on the combination of attributes, and issuing the payment coin in exchange for a first asset. Each attribute of the combination of attributes may represent a different portion of a total value of the payment coin. A partially spent value of the payment coin may be based on a revealed subset of the combination of attributes. The method further includes creating a refund coin based on the combination of attributes and spending the refund coin to issue a refund having a value corresponding to an unspent portion of the payment coin. Each attribute of the combination of attributes of the refund coin may represent a different portion of a total value of the refund coin.

Abstract: A data processing system includes a system interconnect, a first master, and a bridge circuit. The bridge circuit is coupled between the first master and the system interconnect. The bridge circuit is configured to, in response to occurrence of an error in the first master, isolate the first master from the system interconnect, wherein the isolating by the bridge circuit is performed while the first master has one or more outstanding issued write commands to the system interconnect which have not been completed. The bridge circuit is further configured to, after isolating the first master from the system interconnect, complete the one or more outstanding issued write commands while the first master remains isolated from the system interconnect.

Abstract: An integrated circuit including a comparator having a first input to receive a reference voltage, a second input, and an output to provide an under-voltage indicator. Sense points are configured to provide a plurality of sense point voltages, each sense point providing a corresponding sense point voltage of the plurality of sense point voltages; and a minimum voltage tracking circuit configured to receive the plurality of sense point voltages and provide an output voltage which tracks whichever sense point voltage of the plurality of sense point voltages is currently a minimum sense point voltage. The comparator receives the output voltage at the second input and asserts the under-voltage indicator when the output voltage is below the reference voltage.

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

Abstract: A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.

Abstract: A method is provided for watermarking a machine learning model used for object detection or image classification. In the method, a first subset of a labeled set of ML training samples is selected. The first subset is of a predetermined class of images. In one embodiment, the first pixel pattern is selected and sized to have substantially the same dimensions as each sample of the first subset or each bounding box in the case of an object detector. Each sample of the first subset is relabeled to have a different label than the original label. An opacity of the pixel pattern may be adjusted independently for different parts of the pattern. The ML model is trained with the labeled set of ML training samples and the first subset of relabeled ML training samples. Using multiple different opacity factors provides both reliability and credibility to the watermark.

Abstract: Various embodiments relate to an inline encryption engine in a memory controller configured to process data read from a memory, including: a first data pipeline configured to receive data that is plaintext data and a first validity flag; a second data pipeline having the same length as the first data pipeline configured to: receive data that is encrypted data and a second validity flag; decrypt the encrypted data from the memory and output decrypted plaintext data; an output multiplexer configured to select and output data from either the first pipeline or the second pipeline; and control logic configured to control the output multiplexer, wherein the control logic is configured to output valid data from the first pipeline when the second pipeline does not have valid output decrypted plaintext data available.

Abstract: A radar system, apparatus, architecture, and method are provided with a transmitter that produces a plurality of distinct FanTOM signals that are transmitted as N RF-encoded transmit signals in an overlapped fashion such that the pulse repetition interval and frame length are kept short; a receiver that processes target return signals reflected from the N RF-encoded transmit signals with a mixer to produce an IF signal which is filtered with one or more notch filters clocked with a sampling clock frequency to control harmonic notch frequencies to suppress transmitter spill-over and close-in self-clutter interference, thereby producing a filtered IF signal that is converted to a digital signal with an analog-to-digital converter that is clocked with the sampling clock frequency; and a radar processor that processes the digital signal to generate a range spectrum comprising N segments that correspond, respectively, to the N RF-encoded transmit signals.

Abstract: A method for protecting a machine learning model is provided. In the method, a first machine learning model is trained, and a plurality of machine learning models derived from the first machine learning model is trained. Each of the plurality of machine learning models may be different from the first machine learning model. During inference operation, a first input sample is provided to the first machine learning model and to each of the plurality of machine learning models. The first machine learning model generates a first output and the plurality of machine learning models generates a plurality of second outputs. The plurality of second outputs are aggregated to determine a final output. The final output and the first output are classified to determine if the first input sample is an adversarial input. If it is adversarial input, a randomly generated output is provided instead of the first output.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a method of communications involves at a communications device, receiving a request for changing a network parameter of the communications device and at the communications device, granting or denying the request based on link status information that is stored in the communications device, where the link status information specifies a link failure status of a communications link within a wired communications network that involves the communication device.

Abstract: Various embodiments relate to a circuit system, including: an original circuit; a dual circuit, wherein the dual circuit is a dual of the original circuit; an input inverter connected the dual circuit, wherein the input inverter inverts system inputs; an output inverter connected to one of the original circuit and the dual circuit, wherein the output inverter inverts the output of the connected original circuit or dual circuit; and a comparator receiving and comparing the output of the invertor and the output of one of the original circuit and the dual circuit not connected to the inverter, wherein the comparator indicates an error when the received outputs are not identical and indicating no error when the received outputs are identical.