Abstract: A method and apparatus are described for a reconfigurable architecture analog front end architecture for electrochemical sensors. In one example, an analog front end includes an electrode driver stage coupled to electrodes of an electrochemical sensor, and measurement channels coupled to the electrode driver stage to receive an electrode signal from the electrodes of the electrochemical sensor and to generate measurement results, the measurement channels configured to switch configurations to perform different measurements.

Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

Abstract: A method is described for analyzing an output of an object detector for a selected object of interest in an image. The object of interest in a first image is selected. A user of the object detector draws a bounding box around the object of interest. A first inference operation is run on the first image using the object detector, and in response, the object detect provides a plurality of proposals. A non-max suppression (NMS) algorithm is run on the plurality of proposals, including the proposal having the object of interest. A classifier and bounding box regressor are run on each proposal of the plurality of proposals and results are outputted. The outputted results are then analyzed. The method can provide insight into why an object detector returns the results that it does.

Abstract: Various embodiments relate to a memory controller configured to read data from a memory array, including: an error correction codes (ECC) encoder configured to encode data stored in the memory array; an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and a fault controller configured to: command the memory controller to read other data from the memory array when the ECC detects an error; command the memory controller to re-read the first data from the memory array; when the ECC detects an error; compare the re-read first data to the read first data; and signal a fault attack when the re-read first data is different from the read first data.

Abstract: A true random number generator circuit includes a ring oscillator and a plurality of sampling circuits. The ring oscillator includes a plurality of series-connected stages coupled together in a ring. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. A sampling circuit of the plurality of sampling circuits has an input coupled to a node located between two adjacent stages of the plurality of series-connected stages. Every node of the ring oscillator is coupled to a corresponding sampling circuit of the plurality of sampling circuits. In another embodiment, a method for generating a random number is provided.

Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.

Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.

Abstract: Embodiments of an antenna system and a method for operating an antenna are disclosed. In an embodiment, an antenna system includes a first ferrite element, a second ferrite element, a first coil wrapped around the first ferrite element, a second coil wrapped around the second ferrite element, a first antenna interface electrically coupled to the first coil, a second antenna interface electrically coupled to the second coil, and a conductor network connected between the first coil, the second coil, the first antenna interface, and the second antenna interface.

Abstract: Various embodiments relate to a memory controller configured to read data from a memory array, including: an error correction codes (ECC) encoder configured to encode data stored in the memory array; an ECC decoder configured to decode first data read from the memory array based upon a first read request and detect errors in the first data read from the memory array; and a fault controller configured to: command the memory controller to read other data from the memory array when the ECC detects an error; command the memory controller to re-read the first data from the memory array; when the ECC detects an error; compare the re-read first data to the read first data; and signal a fault attack when the re-read first data is different from the read first data.

Abstract: A voltage glitch detector includes a ring oscillator, a plurality of counters, a combined result circuit, and a result evaluation circuit. The ring oscillator includes a plurality of series-connected stages. An output of a last stage of the ring oscillator is coupled to an input of a first stage of the ring oscillator. Each counter of the plurality of counters has an input coupled to a node located between two stages of the plurality of series-connected stages. The combined result circuit is coupled to each of the plurality of counters. The combined result circuit combines the count values received from each counter of the plurality of counters to provide a combined result. The result evaluation circuit is coupled to compare the combined result with a reference value to determine when a voltage glitch is detected.

Abstract: A first error is determined between a bandgap reference output voltage of a bandgap reference circuit at a first temperature and a target voltage. A second temperature of the bandgap reference circuit is measured. A bandgap reference output voltage of the bandgap reference circuit is predicted at the second temperature and based on the first error. A second error is determined between the bandgap reference output voltage and the target voltage. A trim parameter of the bandgap reference circuit is determined based on the second error. The bandgap reference circuit is set with the trim parameter, where a third error between a bandgap reference output voltage of the bandgap reference with the trim parameter is less than the second error.

Abstract: In accordance with a first aspect of the present disclosure, a system is provided for facilitating detecting an unauthorized access to an object, the system comprising: a plurality of ultra-wideband (UWB) communication nodes; a controller operatively coupled to said plurality of UWB communication nodes, wherein the controller is configured to: cause at least one of the UWB communication nodes to transmit one or more UWB messages to other UWB communication nodes of said plurality of UWB communication nodes; receive a channel impulse response (CIR) estimate and/or one or more parameters relating to said CIR output by the UWB communication nodes in response to receiving said UWB messages; analyze said CIR estimate and/or said parameters relating to the CIR to detect said unauthorized access to the object. In accordance with a second aspect of the present disclosure, a corresponding method is conceived for facilitating detecting an unauthorized access to an object.

Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: an ultra-wideband (UWB) transceiver configured to communicate with an external communication device; a processing unit configured to switch the UWB transceiver between different transceiver modes of operation while the UWB transceiver receives or transmits a data frame; wherein the different transceiver modes of operation include a ranging mode, an angle-of-arrival (AoA) mode and/or a radar mode. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: A system and method for a memory system are provided. A memory device includes an array of non-volatile memory cells. A memory controller is connected to the array of non-volatile memory cells. The memory controller is configured to perform the steps of receiving a request to read a value of a memory flag, wherein the memory flag includes a 2-bit value stored in a first memory cell and a second memory cell of the array of non-volatile memory cells, reading a first value of the first memory cell, reading a second value of the second memory cell, and determining the value of the memory flag based on the first value and the second value. In embodiments, the memory flag may have more than 2-bits.

Abstract: A communications system (300) comprising: an antenna (320) that comprises a plurality of serially connected sub-antenna elements (322); and a signal generator (324) configured to provide a transmission signal to the antenna (320) for propagating along the sub-antenna elements (322). The transmission signal comprises a plurality of serial symbol packets. The signal generator (324) is configured to set the phase of the serial symbol packets such that when they align with predefined ones of the sub-antenna elements (322) the antenna (322) provides a beamformed signal.

Abstract: Design and methods for implementing a Rational Ratio Multiplier (RRM) with close to 50% duty cycle. This invention gives an optimal way to implement an RRM that saves both area and power for a given design and is able to achieve a good accuracy of the output clock with a difference between the high period and the low period of the output clock by only half a cycle of the input clock which is the closest to get to a 50% duty cycle clock.

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: A temperature sensor includes a sensing element and a load. Multiple different currents pass through the sensing element in a sequential manner. Based on each current that passes through the sensing element, the sensing element outputs a complementary-to-absolute-temperature (CTAT) voltage and another current. Further, the currents that pass through the sensing element and the currents that the sensing element output separately pass through the load and result in the generation of multiple load voltages across the load. A current density ratio of the temperature sensor is determined based on the load voltages generated across the load. Further, a temperature value indicative of a temperature sensed by the temperature sensor is generated based on the current density ratio and the CTAT voltages outputted by the sensing element based on the different currents that pass therethrough.

Abstract: In one example, a radar circuit uses computer processing circuitry for processing data corresponding to reflection signals via a sparse array. Output data indicative of signal magnitude associated with the reflection signals is generated, and then angle-of-arrival information is discerned therefrom by (e.g., iteratively): correlating the output data with at least one spatial frequency support vector indicative of a correlation peak for the output data; generating upper-side and lower-side support vectors which are neighbors along the spatial frequency spectrum for said at least one spatial frequency support vector, and providing, via a correlation of the upper-side and lower-side support vectors and said at least one spatial frequency support vector, at least one new vector that is more refined along the spatial frequency spectrum for said at least one spatial frequency support vector.

Abstract: A register management system is coupled to a register. The register management system receives an address and functional data for a write operation to be performed on the register. The functional data includes write bits and mask bits associated with the write bits. One or more mask bits having a first logic state indicate that associated one or more write bits are to be written to the register, respectively. Based on the address, the register management system selects a first half of the register or a second half of the register to perform the write operation. Further, the register management system writes the one or more write bits associated with the one or more mask bits having the first logic state to one or more storage elements of the first half of the register or the second half of the register, respectively.