Abstract: Various embodiments relate to a buck-boost converter controller configured to control a buck-boost controller, wherein the buck-boost converter has a buck mode of operation, a boost mode of operation, and a buck-boost mode of operation, including: a phase controller configured to produce phase control signals to control switching in the buck-boost converter, wherein the phase control signals are based on a mode of operation of the buck-boost converter; and an automatic mode selector configured to indicate to the phase controller the mode of operation of the buck-boost controller based upon a buck on-time TON_bk or a buck off-time TOFF_bk, a boost on-time TON_bst or a boost off-time TOFF_bst, and a control configuration on-time TPI3, where TON_bk is the on-time during the buck mode of operation, TOFF_bk is the off-time during the buck mode operation, TON_bst is the on-time during the boost mode of operation, TOFF_bk is the off-time during the boost mode operation, and TPI3 is the time where a second high-side

Abstract: It is described a voltage regulator device (100), comprising: i) a power device (150), configured to receive an input signal (151) and to produce a corresponding output signal (152); ii) a comparator device (110), coupled via a feedback path (140) to the power device (150), and configured to receive the output signal (152) as a feedback signal (141), and to produce a compared feedback signal (112); and iii) a digital modulation device (120), arranged between the comparator device (110) and the power device (150), and configured to digitally modulate the compared feedback signal (112), and to provide the digitally modulated signal (121) to the power device (150), wherein the digital modulation device (120) comprises: iiia) a delta-sigma (122), iiib) a quantizer (124), and iiic) a feedforward path (128), configured to feedforward the compared feedback signal (112) beyond the delta-sigma (122).

Abstract: Phase noise reduction is described for symmetric bistatic radar. In one example, a first beat signal is generated of a second signal received at a first antenna and a third beat signal is generated at a second antenna of a first linear antenna array. A second beat signal is generated of a first signal received at a first antenna of a second linear antenna array. The first beat signal and the third beat signal are multiplied with the complex conjugate of the second beat signal to generate products that are combined to generate a phase estimation correction term that is applied to first and second sets of radar return signals.

Abstract: A data processing system and method for norm checking a cryptographic operation for lattice-based cryptography in a processor, the instructions, including: multiplying a first polynomial by a second polynomial to produce a first output, wherein the d arithmetic shares have a modulus q?; securely converting the first output to d Boolean shares; securely subtracting a third polynomial from the first output to produce a second output, wherein the third polynomial is randomly generated and then offset by a first constant parameter; securely adding a first constant based upon a bound check and the first constant parameter to the second output to shift the values of the second output to positive values to produce a third output; and securely adding a second constant based upon the bound check to the third output to produce a carry bit.

Abstract: A virtualized controller area network (CAN) system including multiple virtual CAN controllers and a CAN virtual network controller. The CAN virtual network controller includes virtual CAN interfaces, network interfaces, and a configuration controller. Each of the virtual CAN interfaces communicatively links each virtual CAN controller with the network interfaces, which are each configured to communicatively link one or more of virtual CAN controllers into a CAN network. The configuration controller programs any one or more of the network interfaces to communicatively link any one or more of the virtual CAN controllers in each of one or more CAN networks. The configuration controller configures a network interface for virtual communications for implementing a virtual CAN network, or enables a linked physical protocol engine for implementing a physical CAN network. The number of protocol engines needed, if any, may be significantly reduced thereby reducing pin count and silicon area consumption.

Abstract: The present invention relates to radar systems and associated methods of operation. In one aspect, the present invention relates to an automotive radar system including at least one receiver configured to receive radar signals, a processing system configured to receive from at least one receiver, a received radar signal, process the received radar signal to generate a data frame that has dimensions of M rows by M columns of elements from a covariance matrix, determine a rank N of the data frame. The system is further configured to set all elements in a first subset of columns numbered N through M of the data frame to zero values to create a padded data frame, calculate a pseudo-inverse value of the padded data frame, determine a direction of arrival of at least one target using the pseudo-inverse value, and control an operation of a vehicle using the direction of arrival.

Abstract: A system and method of responding to fuzzing including receiving a fuzzing input while in fuzzed mode, performing a perceptual hashing function using the fuzzing input to generate a perceptual hash value, selecting an action from a list of actions using the perceptual hash value, and performing the selected action in response to the fuzzing input. Parameters may be generated using the perceptual hash value for actions that use parameters. Instead of normal hashing, perceptual hashing generates the same hash value for substantially similar fuzzing inputs so that corresponding fuzzing response actions appear to be random but instead are intentional. Hardware or software version numbers may be combined with a shared secret key and hashed using a non-perceptual hashing function to further impede comparison analysis by a fuzzer. Some embodiments combine perceptual hashing with non-perceptual hashing, such as cryptographic hashing or the like.

Abstract: A method is provided for detecting a proximity of a radio frequency (RF) field during an ongoing RF activity by a wireless device operating in reader mode. In the method, an input signal is modulated to provide a modulated RF signal comprising a plurality of RF modulation periods. The plurality of RF modulation periods are transmitted by the wireless device operating in the reader mode. An RF detector is enabled to monitor the plurality of modulation periods during the transmitting of the plurality of RF modulation periods. An external RF signal is detected when a characteristic of the plurality of RF modulation periods is different from an expected characteristic. In another embodiment, a wireless device is provided that implements the method.

Abstract: A method is provided for watermarking a machine learning model. A sequence of bits is generated. The sequence of bits may be text characters divided into chunks. A selected plurality of input samples from training data is divided into subsets of input samples. All of the input samples of each subset of the subsets of input samples are labeled with a same first label in a problem domain of the ML model. Each chunk is combined with a subset of the labeled subsets to produce a plurality of labeled trigger samples. Each trigger sample of each set of the plurality of sets is relabeled to have a second label different from the first label and in the problem domain to produce a relabeled set of trigger samples. The ML model is trained with the training data and the relabeled trigger samples to produce a watermarked ML model.

Abstract: A dynamic element matching system including sequential register groups, decode circuitry, and pointer control circuitry. Each register group includes at least two registers. The decode circuitry controls a state of each register group based on a level of a digital input signal, a relative position with respect to a begin pointer and an end pointer, and a corresponding one of multiple pseudo random probability values. The pointer control circuitry cyclically advances the end pointer among the register groups causing decode circuitry to add one or more register groups and enable a register within each added register group in response to the level of the digital input signal increasing, and also cyclically advances the begin pointer among the register groups causing the decode circuitry to remove one or more register groups and disable a register within each removed register group in response to the level of the digital input signal decreasing.

Abstract: In accordance with a first aspect of the present disclosure, a radio frequency (RF) communication device is provided, comprising: a receiver unit configured to receive at least one radio frequency signal, wherein the receiver unit has a variable initial phase; a controller configured to change said initial phase; a measurement unit configured to measure a plurality of amplitudes and/or phases of the radio frequency signal, wherein each of said amplitudes and/or phases of the radio frequency signal corresponds to a different initial phase of the receiver unit. In accordance with a second aspect of the present disclosure, a corresponding method of operating an RF communication device is conceived.

Abstract: A method of generating an audible alert by a digital audio system configured to operate in a first operating mode and a second operating mode is described. An alert signal is generated or received. One or more segments of the generated or received alert signal is processed. The processed alert signal is then analysed to define the operating mode of the digital audio system. In the first operating mode, the alert output signal includes at least the alert signal. In the second operating mode, the alert output signal includes at least the processed alert signal.

Abstract: A two-stage test process for testing IC packages having integrated launchers includes a first stage in which an RF-accurate test process is used to perform RF-accurate tests on a sample set of IC packages to obtain RF-accurate test results and a loop-back test process is performed to obtain loop-back test results. Test characterization data is obtained by comparing the RF-accurate test results to the loop-back test results. In a second stage, larger-scale testing is performed solely with the loop-back test process, and the loop-back test results for each tested IC package are compared with the test characterization data to characterize the test operation of the tested IC package. The loop-back test process can employ a test jig employing a PCB-mounted or PCB-integrated loop-back structure for relatively rapid test setup and test processing.

Abstract: One example discloses a voltage converter, including: a power stage configured to generate an output voltage (Vo) and an output current (Jo) based on a switching frequency (fs); a primary control loop configured to vary the switching frequency (fs) in response to an on-time value code (Ton_code) and/or a peak output current code (iLpeak_code); and a secondary control loop configured to generate the Ton_code and/or the iLpeak_code.

Abstract: A radio detection and ranging (radar) system includes various antennas and a controller. The antennas receive an interfering radio wave in an operating beamwidth of the radar system. The operating beamwidth is divided into a plurality of sectors. The controller determines a direction-of-arrival and a power level of the interfering radio wave. Further, the controller determines a power level of received signal energy within each sector of the plurality of sectors, and selects, from the plurality of sectors, a set of sectors such that a power level of received signal energy within each sector of the set of sectors is less than a threshold value of the corresponding sector. The controller then broadcasts another radio wave within the selected set of sectors to mitigate the interference of the interfering radio wave.

Abstract: A non-volatile memory (NVM) system includes a memory array divided into physical pages, control circuitry, and a global transaction log (GTL). Each physical page is configured to store a corresponding payload and corresponding metadata for the physical page. Each entry of the GTL is configured to store a transaction descriptor identifying a transaction and a corresponding physical page used by the transaction. Each entry also has a corresponding transaction log entry (TLE) flag. The control circuitry is configured to populate the entries of the GTL in sequential order with each new transaction, and, in response to completing storing the transaction descriptor for a new transaction, program the corresponding TLE flag by toggling its logic state.

Abstract: Aspects of the subject disclosure may include, for example, remapping a first address bus into a first remapped address bus by replacing bit lines of the first address bus with attribute bit lines, the first remapped address bus supplying updated address information, connecting the first address remapped bus to an address translation unit (ATU), the ATU configured to translate the updated address information into translated address information supplied to a second address bus, and remapping the second address bus into a second remapped address bus by replacing a portion of the second address bus with the bit lines of the first address bus that were replaced by the attribute bit lines, the second remapped address bus changing the translated address information into updated translated address information.

Abstract: A non-volatile memory (NVM) includes a daisy chained normal read bus, a daisy chained verify read bus, and a plurality of partitions. Each partition includes a portion of the daisy chained normal read bus and a portion of the daisy chained verify read bus. A memory controller receives read data in response to normal read access requests to the NVM via the daisy chained normal read bus and, in response to write access requests to the NVM, receives verify read data via the daisy chained verify read bus. A bus sharing circuit is coupled between a first partition and a second partition. The bus sharing circuit, in response to a sharing control signal, selectively repurposes portions of the daisy chained verify read bus in at least one of the partitions to communicate read data to the memory controller in response to a normal read access request to the NVM.

Abstract: Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the method includes sending, from a first antenna device of a base station (BS), a plurality of first wireless communication signals respectively during a first plurality of time periods associated respectively with a first plurality of symbols and also a plurality of first wireless sensing signals respectively during a second plurality of time periods associated respectively with a second plurality of symbols. Also, the method includes receiving, at the antenna device, a plurality of second wireless communication signals respectively during a third plurality of time periods associated respectively with a third plurality of symbols and also a plurality of second wireless sensing signals respectively during the second plurality of time periods. The second plurality of time periods are interleaved among respective pairs of the first plurality of time periods.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over the upper surface of the semiconductor substrate, and a first current-carrying electrode and a second current-carrying electrode formed over the semiconductor substrate within openings formed in the first dielectric layer. A control electrode is formed over the semiconductor substrate and disposed between the first current-carrying electrode and a second current-carrying electrode and over the first dielectric layer. A first conductive element is formed over the first dielectric layer, adjacent the control electrode and between the control electrode and the second current-carrying electrode. A second dielectric layer is disposed over the control electrode and over the first conductive element. A second conductive element is disposed over the second dielectric layer and over the first conductive element.