Patents Assigned to NXP B.V.
  • Patent number: 11909851
    Abstract: A packet is transmitted from a remote device over a communication network. A fragment detector detects one or more fragments in a field of the packet, where the field is associated with a session layer or higher abstraction layer of an open systems interconnect (OSI) model. Fragment information is extracted from the packet which indicates one or more of a last fragment index associated with a last fragment of one or more fragment in the packet and a fragment count indicative of a number of fragments associated with a message which is fragmented. Interrupts associated with the packet with other interrupts associated with other packets are coalesced based on one or more of the last fragment index and the fragment count.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: February 20, 2024
    Assignee: NXP B.V.
    Inventors: Jochen Seemann, Andrei Sergeevich Terechko
  • Patent number: 11902406
    Abstract: A system for data communication between electronic devices comprises a first electronic device that is a resource-constrained device; and a second electronic device that exchanges data with the first electronic device. One of the first electronic device and the second electronic device generates a message in a data unit frame complying with a protocol stack that includes a Constrained Application Protocol (CoAP) message on a data link layer in the absence of a User Datagram Protocol (UDP) layer.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: February 13, 2024
    Assignee: NXP B.V.
    Inventor: Christian Herber
  • Patent number: 11901414
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor region of a first semiconductor type, formed within the semiconductor substrate, wherein the first semiconductor region includes a first doped region formed in a lower portion of the first semiconductor region and a second doped region formed over the first doped region in an upper portion of the first semiconductor region. A defect layer having an upper surface formed in an upper portion of the first doped region. A second semiconductor region of a second semiconductor type is formed over the first semiconductor region.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: February 13, 2024
    Assignee: NXP B.V.
    Inventors: Ljubo Radic, Viet Thanh Dinh, Petrus Hubertus Cornelis Magnee
  • Patent number: 11893843
    Abstract: In accordance with a first aspect of the present disclosure, a communication node is provided, comprising: an ultra-wideband (UWB) communication unit configured to enable UWB communication with a plurality of external communication nodes; a processing unit configured to perform ranging sessions between the communication node and said external communication nodes, wherein said ranging sessions comprise one or more distance measurements based on messages exchanged through the UWB communication unit between the communication node and said external communication nodes; and a prioritization unit configured to prioritize said ranging sessions in dependence on at least one previously measured distance between the communication node and the respective external communication nodes. In accordance with a second aspect of the present disclosure, a method of operating a communication node is provided.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: February 6, 2024
    Assignee: NXP B.V.
    Inventors: Michael Schober, Christian Eisendle, Stefan Lemsitzer
  • Patent number: 11886216
    Abstract: A voltage regulator is provided. The voltage regulator includes a shunt transistor and a feedback circuit. The shunt transistor has a first current electrode coupled to a first voltage source terminal, a second current electrode coupled to a second voltage source terminal, a control electrode coupled to receive a reference voltage, and a body electrode. The feedback circuit has an input terminal coupled to the body electrode of the shunt transistor, and an output terminal coupled to the control electrode of the shunt transistor. The voltage regulator is suitable for use in a passive RFID device to protect the device from over-voltage damage. In another embodiment, a method for regulating a voltage is provided.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: January 30, 2024
    Assignee: NXP B.V.
    Inventors: Ivan Jesus Rebollo Pimentel, Thomas Pichler, Ronald van Langevelde
  • Patent number: 11888215
    Abstract: An antenna system for a mobile communications base station and a method of operating a communications network including a base station is described. The antenna system includes an antenna array for beamforming and is configured either as a radar sensor, a communications antenna or a combined radar sensor. A radar image may be used to determine a map of objects in the vicinity of the antenna system and to adapt the beam-steering or beamforming of the antenna system.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: January 30, 2024
    Assignee: NXP B.V.
    Inventors: Paul Mattheijssen, Konstantinos Doris, Dominicus Martinus Wilhelmus Leenaerts, Mark Tomesen
  • Patent number: 11888866
    Abstract: A security module (460) for a CAN node (402). The security module (460) comprises: a RXD input interface for receiving data from a CAN bus (404), and a TXD output interface for transmitting data to the CAN bus (404). The security module (460) is configured to: receive a CAN frame from the CAN bus via the RXD input interface; compare an identifier of the received CAN frame with at least one identifier associated with a local controller (410); and upon detection of a match between the identifier of the received CAN frame and the at least one identifier associated with the local controller (410), output an error signal to the CAN bus via the TXD output interface by setting a predetermined plurality of consecutive bits (682) in the CAN frame to a dominant value. The predetermined plurality of consecutive bits (682) identifies a security error to CAN nodes connected to the CAN bus (404) and is at least 10 consecutive bits.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 30, 2024
    Assignee: NXP B. V.
    Inventor: Bernd Uwe Gerhard Elend
  • Patent number: 11888204
    Abstract: A transmission line includes a signal conductor and one or more return conductors, one or more of which having a stepped multi-layer structure. The return conductors may be disposed at opposite sides of the signal conductor. The return conductors may be multi-layer structures. At least some layers of each return conductor may have a stepped arrangement that defines a curve, such as an exponential curve. Additionally or alternatively, the signal conductor may be a stepped multi-layer structure, where at least some layers of the signal conductor may define a curve, such as an exponential curve. The signal conductor may be disposed at one or more upper layers of the transmission line or may be embedded at one or more layers near the center of the transmission line.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: January 30, 2024
    Assignee: NXP B.V.
    Inventors: Mustafa Acar, Danny Wayling Chang, Dominicus Martinus Wilhelmus Leenaerts, Philipp Franz Freidl
  • Patent number: 11888659
    Abstract: There is described an RFID IC, comprising: i) an RFID interface configured to receive a digitally modulated signal, wherein the digitally modulated signal comprises: a first slot with a first pulse, and a second slot with a second pulse; and ii) a processing unit configured to a) determine a first position of the first pulse in the first slot, b) filter a region that follows the determined first position of the first pulse, c) determine a second position of the second pulse in the second slot, and, if the second position of the second pulse cannot be determined in the second slot, assume that the second position of the second pulse in the second slot is at the filtered region.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: January 30, 2024
    Assignee: NXP B.V.
    Inventors: Christian Weidinger, Heinz Umfahrer
  • Patent number: 11882455
    Abstract: In accordance with the first aspect of the present disclosure, an ultra-wideband communication node is provided, comprising: an ultra-wideband communication unit configured to transmit one or more ultra-wideband frames to an external device; a processing unit configured to determine scrambled timestamp sequences for said ultra-wideband frames; wherein the processing unit is further configured to determine designated time slots, within which said scrambled timestamp sequences are to be received by said external device.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: January 23, 2024
    Assignee: NXP B.V.
    Inventors: Michael Schober, Ulrich Andreas Muehlmann, Hugues Jean Marie de Perthuis
  • Patent number: 11879990
    Abstract: In one example, a continuous-wave radar circuit receives reflection signals, computer processing circuitry processes data corresponding to the reflection signals, and emulation circuitry introduces a plurality of diagnostic data sets into the radar circuit to cause the radar circuit to process simulated reflection signals as though the simulated reflection signals are reflections from objects remote from the apparatus. The radar circuit may receive the reflection signals in response to chirp sequences actually transmitted as reflections from objects.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 23, 2024
    Assignee: NXP B.V.
    Inventors: Haridas Vilakathara, Kai Peter Ludwig Gossner, Artur Tadeusz Burchard
  • Patent number: 11881425
    Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.
    Type: Grant
    Filed: October 18, 2022
    Date of Patent: January 23, 2024
    Assignee: NXP B.V.
    Inventors: Antonius Hendrikus Jozef Kamphuis, Guido Albermann, Johannes Cobussen
  • Patent number: 11879939
    Abstract: An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: January 23, 2024
    Assignee: NXP B.V.
    Inventors: Nikila Krishnamoorthy, Abhishek Mahajan, Rishabh Kaistha, Varsha Bansal
  • Patent number: 11882414
    Abstract: There is disclosed an audio playback system including a loudspeaker, a microphone and a means for implementing a method of detecting a fault which includes the generation and analysis of a specific ultrasound reference signal. The presence of the ultrasound reference signal can be detected on the microphone signal, and the signal-to-noise ratio can be estimated during the reference signal playback so that the volume of the reference signal can be adapted if necessary. The reference signal is a multi-sinusoidal signal which, when averaged over time increases the expected signal-to-noise ratio, and hence, the power of the detector.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: January 23, 2024
    Assignee: NXP B.V.
    Inventor: Temujin Gautama
  • Patent number: 11876726
    Abstract: Cut-through frame transfer or store-and-forward frame transfer of a frame in an network switch is disclosed. A frame is received from an input port of the switch. A time period in a cycle time when the frame is received and a stream identification of the frame is determined. One of the cut-through frame transfer and the store-and-forward frame transfer of the frame is performed based on the time period in the cycle time when the frame was received and the stream identification.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventors: Bernard Francois St-Denis, Sathish Vallipuram
  • Patent number: 11876486
    Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventors: Siyaram Sahu, Anand Kumar Sinha, Ateet Omer, Krishna Thakur
  • Patent number: 11875214
    Abstract: In accordance with a first aspect of the present disclosure, a radio frequency identification (RFID) transponder is provided, comprising: a receiver configured to receive a command from an external RFID reader, wherein the command is a first command transmitted by the RFID reader during a communication session and wherein said command comprises a at least one parameter indicative of one or more modifiable settings of the RFID transponder; and a controller configured to modify the settings of the RFID transponder in accordance with a value of said parameter. In accordance with a second aspect of the present disclosure, a corresponding method of operating a radio frequency identification (RFID) transponder is conceived.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventors: Thomas Pichler, Ivan Jesus Rebollo Pimentel
  • Patent number: 11875619
    Abstract: An infrastructure-controller for an infrastructure. The infrastructure-controller configured to: send a ranging-scheduling-signal to a key, wherein the ranging-scheduling-signal comprises timing-information for a subsequent ranging operation; and activate one or more ranging nodes associated with the infrastructure, for receiving a key-ranging-signal from the key, at an infrastructure-node-start-ranging-time based on the timing-information. The ranging-scheduling-signal has a frequency in a first RF frequency range. The key-ranging-signal has a frequency in a second RF frequency range.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventors: Mehmet Ufuk Buyuksahin, Wolfgang Eber, Dorian Haslinger
  • Patent number: 11877256
    Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for determining the position of at least one node in a communication network, wherein the communication network comprises a localization system that includes a processing unit, a primary anchor and at least one secondary anchor, the method comprising: the primary anchor transmits a poll message to the node and to the secondary anchor; the primary anchor receives a response message from the node; the secondary anchor receives said poll message from the primary anchor and said response message from the node; the processing unit calculates the position of the node using position information and timing information, wherein said position information is position information of the primary anchor and of the secondary anchor, and wherein said timing information is timing information of the poll message transmission by the primary anchor, of the poll message reception by the node and the secondary anchor, of the response message transmi
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventors: Michael Schober, Christian Eisendle, Ghiath Al-kadi
  • Patent number: 11876524
    Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0?), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: January 16, 2024
    Assignee: NXP B.V.
    Inventor: Muhammed Bolatkale