Abstract: A central system coupled to a subsystem receives a fault indication associated with a fault in one or more circuits of the subsystem from a local fault collection and control (FCCS) of the subsystem when a software recovery of the fault fails. Based on the received fault indication, the local FCCS and a central FCCS of a central system is masked from additional fault indications from the one or more circuits. The central system then signals the reset of the one or more circuits of the subsystem after the masking of the additional fault indications, wherein the one or more circuits is reset based on the signaling and the additional faults are masked from one or more of the local FCCS and central FCCS during the reset.

Abstract: One example discloses a power controller [400] configured to modulate a load current sent to a load, including: a first chip [406] including a set of higher-power circuits configured to directly modulate the load current sent to the load [410]; a second chip [404] electrically coupled to the first chip and including a set of lower-power circuits; wherein the set of higher-power circuits are electrically isolated from the set of lower-power circuits; a power control path [212] distributed between the first chip and the second chip, and configured to modulate the load current sent to the load; a diagnostics path [218] distributed between the first chip and the second chip, and configured to monitor the higher-power circuits in the first chip and the lower-power circuits in the second chip for a set of fault conditions; wherein a portion of the diagnostics path in the second chip includes a plausibility circuit [420] configured to compare a load current commanded by a first portion of the power control path in t

Abstract: A linear voltage regulator includes a converter circuit that provides a serial bitstream having a pulse density that is indicative of a difference between a regulated voltage of the linear voltage regulator and a reference voltage. The linear voltage regulator also includes a digital to analog converter circuit that includes an input to receive the serial bitstream. The digital to analog converter circuit includes an averager circuit that produces an output signal to control a voltage of a control terminal of a power transistor of the linear voltage regulator for regulating the regulated voltage based on the pulse density of the serial bitstream.

Abstract: A method is provided for securely provisioning a plurality of integrated circuits (ICs) manufactured by a first entity for use in a plurality of manufactured product types manufactured by a second entity. Each IC of the plurality of ICs includes a key pair and a unique identifier (UID). The first entity generates a plurality of key pairs that are not related to the plurality of ICs. A plurality of product types is received from the second entity. A plurality of certificates is generated by the first entity using the UIDs and the key pairs. The plurality of certificates is transferred from a first computer system of the first entity to a second computer system under physical control of the second entity. The second entity injects the plurality of ICs with selected certificates of the plurality of certificates. Unused certificates may be deleted from the second computer system.

Abstract: An integrated circuit, IC, comprising one or more DC blocking modules connected to a respective input/output, IO, pin of the IC, each DC blocking module comprising: a capacitor having a first terminal connected to the respective IO pin and a second terminal connected to a node of the circuitry of the IC; and an electrostatic discharge, ESD, protection circuit connected in parallel to the capacitor, the ESD protection circuit comprising: a conduction path connected between the first terminal of the capacitor and the second terminal of the capacitor; and a control terminal configured to receive a control signal to switch the ESD protection circuit between: an operational mode in which the conduction path is in a non-conducting state and provides ESD protection to the capacitor; and a test mode in which the conduction path is in a conducting state and short circuits the capacitor.

Abstract: A touch panel system that includes drivers for providing detection signals on a first plurality of electrodes of a touch panel where each detection signal includes one or more frequency signal components with each frequency signal component having a frequency and a phase offset. The detection signals includes at least three phase offsets for at least one frequency of the frequency signal components. Each detection signal has a unique frequency-phase offset combination of the one or more frequency signal components. The unique combinations allow for the determination of a touch at specific locations on the panel by sensing signals on a second set of electrodes.

Abstract: In accordance with a first aspect of the present disclosure, a system is provided for facilitating localizing an external object, the system comprising: a plurality of ultra-wideband (UWB) communication nodes; a controller operatively coupled to said plurality of UWB communication nodes, wherein the controller is configured to: cause at least one of the UWB communication nodes to transmit one or more UWB messages to other UWB communication nodes of said plurality of UWB communication nodes; receive a channel impulse response (CIR) estimate and/or one or more parameters relating to said CIR output by the UWB communication nodes in response to receiving said UWB messages; analyze said CIR estimate and/or said parameters relating to the CIR; select a localization process in dependence on a result of analyzing said CIR estimate and/or said parameters relating to the CIR.

Abstract: A protection circuit and method for protecting driven circuitry against voltage peaks in a radio frequency signal, “VRF”, past a predetermined voltage level “Vdetect”. The protection circuit includes an input for receiving the radio frequency signal. The protection circuit also includes at least one amplification stage coupled to the input. The amplification stage is operable to produce an amplified signal based on Vdetect?VRF. The protection circuit further includes a hold circuit operable to determine, from the amplified signal produced by the amplification stage, whether a peak voltage Vpeak of the radio frequency signal exceeds Vdetect. The hold circuit is operable to output a first detection value if Vpeak exceeds Vdetect. The hold circuit is operable to output a second detection value if Vpeak does not exceed Vdetect. The protection circuit also includes a latch circuit operable to latch the detection value outputted by the hold circuit.

Abstract: A mechanism is provided to reduce interference between vehicular radar systems through communicating radar parameters and physical orientation between vehicles and then using directional information to form clusters of radars, which will have consistent modulation parameters. Radar modulation parameters, such as starting frequency, center frequency, bandwidth, slope, ramp direction, timing, and the like for frequency-modulated continuous-wave (FMCW) radars, are adjusted to reduce or eliminate inter-cluster direct interference between clusters oriented in different directions. For other types of radars, in some embodiments, other operational parameters can be adjusted. In some embodiments, some modulation parameters also can be adjusted to reduce or eliminate intra-cluster indirect interference.

Abstract: An SoC with a multiple level resource isolation system including initiator devices that conduct transactions with addressed slave devices via an interconnect, access identifier assignment (AIDA) devices that append an access identifier (AID) including a group identifier (GID) and a domain identifier (DID) to each transaction of a corresponding initiator device, access control (AC) devices that control access to slave devices based on an AID provided with a transaction, a partition manager that programs GIDs into the AIDA and AC devices for assigning slave devices to groups, and group managers that program DIDs into the AIDA devices for each matching GID programmed therein, and that program the AC devices with access rights to one or more DIDs for each slave device assigned to a corresponding group with a matching GID programmed therein.

Abstract: systems and methods include a transmitter with a control unit that is configured to generate a code, including data identifying a plurality of regions and a transmitter-specific cyclic shift scheme. The cyclic shift scheme results in a re-arrangement of the regions (using a change of time offset) that is different (transmitter-specific) for each of the transmitters. The transmitter generates a signal based on the code and transmits the signal via an antenna. The radar system includes a receiver configured to receive an echo of the signal via a second antenna that is reflected from a target and identifies the transmitter from the echo based on the transmitter-specific cyclic shift scheme.

Abstract: A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

Abstract: The disclosure relates to a coding module for an Ethernet transceiver. The coding module may include circuitry configured to: receive data-signaling representative of one or more data words; encode the data-signaling into one or more DC-balanced words each having a DC-balanced-word-length; provide a prepended-word for a first transmission, where a length of the prepended-word is at least as long as the DC-balanced-word-length; and provide the one or more DC-balanced words for a second transmission, where the second transmission is subsequent to the first transmission. The coding module may include circuitry configured to: receive a prepended-word and provide a logic-high signal to an Energy Detect terminal; receive one or more DC-balanced words each having a DC-balanced-word-length; remove a DC-balanced coding from the one or more DC-balanced words to generate data signaling representative of one or more data words; and provide the data signaling to an output terminal.

Abstract: A semiconductor device may include an antenna array and a grounding assembly configured to at least partially electrically shield the antenna array. The grounding assembly may include a first grounding layer comprising a first plurality of openings and a second grounding layer comprising a second plurality of openings. The second grounding layer may at least partially occlude the first plurality of openings of the first grounding layer when viewed from above the antenna array.

Abstract: An architecture for monitoring, analyzing, and reacting to safety and cybersecurity events has been disclosed. In at least one embodiment, a method for processing safety and security events of a system includes requesting a reaction or escalating an effect from a first controller of the system to a second controller of the system based on a subset of available reactions for a current context of the system, constraint information, a predetermined effect-reaction policy, and the effect.

Abstract: Embodiments of systems and methods for estimating direction of arrival are disclosed. A device includes a signal processing unit that includes processing circuitry and memory coupled to the processing circuitry, where the processing circuitry includes multiple vector processing units, each vector processing unit configured to receive an antenna input vector, receive an angular spectrum vector, retrieve a first and second weighting vectors from the memory, generate a processed antenna input vector by performing a circular convolution of the antenna input vector with the first weighting vector, generate a processed angular spectrum vector by performing a circular convolution of the angular spectrum vector with the second weighting vector, and generate a refined angular spectrum vector, which indicates angular position of one or more radar targets, by applying a non-linear activation function to a sum of the processed antenna input vector and the processed angular spectrum vector.

Abstract: The present disclosure relates to a Controller Area Network, CAN, controller, comprising: an input interface, a transmit data, TXD, interface, and a processing unit, wherein the processing unit is configured to receive via the input interface a data packet comprising a packet priority field, a packet payload field, the processing unit is configured to generate a first CAN frame based on the data packet, such that a first payload field of the first CAN frame represents at least the packet payload field and a first identifier field of the first CAN frame includes, a first identifier part representing predefined data for identifying the CAN controller and a second identifier part representing the packet priority field and/or includes a queue field representing a queue priority for the first CAN frame, and the processing unit is configured to send the first CAN frame via the TXD interface.

Abstract: An attenuator arrangement comprising at least a first attenuation path configured to couple between a signal processing chain, SPC, and a measurement apparatus; said SPC comprising a first and second SPC terminal, said SPC configured to apply one or both of a gain and phase change on a signal passed between the SPC terminals; said measurement apparatus configured to measure one or both of the gain and the phase change applied by SPC by coupling to and receiving signals from said SPC terminals; wherein one of said first SPC terminal and said second SPC terminal is coupled to the measurement apparatus through said first attenuation path; and wherein the at least first attenuation path of the attenuator arrangement is configured to provide, selectively, for attenuation of the signal to the measurement apparatus to make the signal power of the signals from said SPC terminals more equal.

Abstract: A method is described for proving erasure of a memory. In the method a prover device receives a seed value from a verifier device. The prover device generates a series of data blocks starting with the seed value and a function. The series of data blocks is generated using the function and the seed to generate a first data block of the series of data blocks. Each subsequent data block is generated using the function and a preceding data block until a last data block of the series of data blocks is generated and written to the memory portion. The prover device writes the series of data blocks to the memory to overwrite all memory contents of a memory portion of the prover device. After the data blocks are written to the memory by the prover device, the prover device sends notification of memory erasure to the verifier device.

Abstract: There is described an analog-to-digital converter, ADC, device (100), comprising: i) a first converter stage (110), comprising a first digital-to-analog converter, DAC, (115), comprising at least two first unit elements (116, 117, 118) each with a first unit element value (U11, U12, U13); ii) a second converter stage (120), comprising a second DAC (125), comprising at least two second unit elements each with a second unit element value (U21, U22, U23); and iii) a control device (180), coupled to the first DAC (115) and the second DAC and configured to: swap at least one of the first unit element values (U1) with at least one of the second unit element values (U2) to obtain corresponding third unit element values (U3) and forth unit element values (U4).