Abstract: A combination of machine learning models is provided, according to certain aspects, by a data-aggregation circuit, and a computer server. The data-aggregation circuit is used to assimilate respective sets of output data from at least one of a plurality of circuits to create a new data set, the respective sets of output data being related in that each set of output data is in response to a common data set processed by the machine learning circuitry in the at least one of the plurality of circuits. The computer server uses the new data set to train machine learning operations in at least one of the plurality of circuits.

Abstract: Near field communication (NFC) methods, systems, and devices are disclosed herein. In an example embodiment, the method includes providing a first NFC device including a NFC antenna, and transmitting a radio frequency (RF) signal including a RF carrier signal by way of the NFC antenna. Also, the method includes receiving a first resonant signal after the transmitting has ceased, and processing the first resonant signal to generate a first portion of transformed signal information. Further, the method includes identifying one or both of a first state and a first event based at least in part upon or associated with the first portion of the transformed signal information.

Abstract: Various embodiments relate to a method for multiplying a first and a second polynomial in a ring q [X]/(Xn+1) where q is a positive integer.

Abstract: A method is provided for collecting diagnostic information in a device having a rich execution environment (REE) and a secure element (SE). The method includes detecting initialization of the device. If it is determined that the initialization of the device was a result of a potential security related event, a communication component of the REE responsible for communicating with the secure element is activated if not already activated. The secure element sends a request to the communication component for diagnostic information related to the security event. The diagnostic information is received in the SE from the communication component and stored in an attack log for storing security events. An attack log is generated in the secure element including the potential security event and the related diagnostic information. The attack log and the related diagnostic information is communicated to a secure server via a secure channel.

Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.

Abstract: A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

Abstract: A microprocessor system includes a processing circuit and a memory operably coupled to the processing circuit and configured to receive input data according to a pack and store operation and output the data according to a load and unpack operation. The processing circuit comprises a hardware extension configured to: configure a variable number of bits per data element during a pack and store operation; store a concatenation of a plurality of data elements with a reduced number of bits; extract a plurality of data elements with a reduced number of bits during a load and unpacking operation; and recreate a plurality of data elements with an increased number of bits per data element representative of the data elements prior to the pack and store operation.

Abstract: A method and system are provided for supplying power to a backup power domain by connecting a battery voltage to a supply terminal for a backup power domain in a low power microcontroller during a startup mode when a main supply voltage, by detecting application of the main supply voltage to the low power microcontroller at a predetermined safe voltage level, and by activating a selection control circuit to power the backup power domain in the low power microcontroller from the main power supply voltage or the backup power supply voltage based on a software-controlled configuration bit, where the selection control circuit is configured to connect, in response to the software-controlled configuration bit having a first user-selected value, the main power supply voltage to the supply terminal for the backup power domain when the main power supply voltage is smaller than the battery power supply voltage.

Abstract: Aspects of the present disclosure are directed toward apparatuses and/or methods involving the communication of radar signals. Certain aspects involve communicating time division multiplexing (TDM) multi-input multi-output (MIMO) radar signals, having pulses with a chirp interval time (CIT) that is different for respective chirps. Positional characteristics of a target may be ascertained based upon both the CIT between each chirp in the communicated radar signals and the time between each corresponding chirp in received ones of the signals reflected by the target. Communication of the radar signals may involve utilizing a combination of antennas to provide a virtual aperture.

Abstract: A method is provided for estimating a signal's angle of arrival (AOA) in a communications system. Starting values for each of a horizontal AOA and a vertical AOA are estimated. The estimated vertical AOA starting value is used to select a horizontal PDOA trace of horizontal PDOA calibration data. The selected horizontal PDOA trace is interpolated to determine a best horizontal AOA estimate for a current iteration. The estimated horizontal AOA starting value is used to select a vertical PDOA trace of vertical PDOA calibration data. The selected vertical PDOA trace is interpolated to determine a best vertical AOA estimate for the current iteration. After each iteration, determining if a maximum number of iterations has been reached or if the best horizontal or vertical AOA estimate has not changed by a predetermined amount. When one of these is true, the best horizontal and vertical AOA estimates are used.

Abstract: A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

Abstract: A receiver comprising: a processing module configured to: receive a first portion of a packet of received signalling from a first antenna; receive a carrier estimate signal; adjust the first portion based on the carrier estimate signal and correlate the signal with an expected code sequence to provide a first correlated signal; a tracking module configured to: receive the first correlated signal and update the carrier estimate signal, wherein the processing module is further configured to: receive a second portion of the packet from a second antenna; adjust the second portion based on the carrier estimate signal and correlate the signal to provide a second correlated signal, and wherein the receive path further comprises a phase calculation module configured to: receive the first and second correlated signals and determine a respective first and second carrier phase and an angle of arrival of the received signalling.

Abstract: A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.

Abstract: In imaging radar, examples are directed to uses of multiple sets of transmit antenna included with transceiver circuitry, for transmitting in a plurality of modes. Transmissions may involve having at least one transmit antenna, from each of at least two of the multiple sets, to transmit continuous-wave energy concurrently (simultaneously) in one or more of the plurality of different modes. Transceiver circuitry may include multiple receive antennas which may be receiving reflections of the continuous-wave energy from various targets. Signals from the multiple receive antennas may route to signal processing circuitry. The signal processing circuitry may respond to the received reflections of the continuous-wave energy by assessing differences in antenna gain and/or phase due to transmit antenna position associated with the received reflections.

Abstract: A sequence recovery method executed by a node in a time-sensitive network, the method comprising receiving a packet having a sequence number, determining whether the sequence number is within a predetermined range of a reference sequence number, wherein the reference sequence number is a current latest sequence number accepted by the node, and wherein the predetermined range comprises a history range and a future range, wherein the history range has a length equal to a history length and includes the reference sequence number and a predetermined number of consecutive sequence numbers that are immediately earlier than the reference sequence number, and the future range has a length equal to a future length and defines a predetermined number of consecutive sequence numbers that are immediately later than the reference sequence number, wherein the future length is greater than the history length.

Abstract: One example discloses a switch mode power supply (SMPS) circuit configured to receive an input voltage and generate an output voltage, including: a set of switching devices configured to receive the input voltage; a first transformer, having an input winding coupled to the switching devices, and an output winding configured to generate the output voltage; a second transformer, having an input winding coupled to receive the output voltage from the first transformer, and an output winding configured to generate an output voltage monitoring signal; and a controller configured to control the switching devices based on the output voltage monitoring signal.

Abstract: A packaged integrated circuit (IC) includes an IC die having first and second external contacts and a package substrate. The IC die is attached to the package substrate which includes a balun in a first metal layer. The balun is connected to the first and second external contacts of the IC die and to a first external contact of the package substrate. The first and second external contacts of the IC die communicate a differential signal with the package substrate, and the first external contact of the package substrate communicates a single-ended signal corresponding to the differential signal. Alternatively, the balun is connected to an external contact of the IC die and to first and second external contacts of the package substrate, in which the external contact of the IC die communicates a single-ended signal and the first and second external contacts of the package substrate communicate a differential signal.

Abstract: A method is provided for identifying or authenticating an object. The method includes vibrating the object at a plurality of frequencies. The vibrations from the object are sensed at each of the plurality of frequencies using an accelerometer. A vibration profile of the object is generated using the sensed vibrations. The generated vibration profile is then compared to a stored vibration profile. It is determined if the generated vibration profile matches the stored vibration profile. A match indicates that the object has been identified or authenticated. In another embodiment, an object capable of implementing the method is provided. In another embodiment, the object may include a replaceable accessary. In this case, the initial and generated vibration profiles may be created with the replacement accessary attached to the object. A match of the generated and initial vibration profiles indicates that the replaceable accessary is authentic.