Abstract: Disclosed is a circuit including timer interleaved (TI) analog-to-digital converter (ADC) circuitry which generates digital output signals. Correction circuitry receives the digital output signals from the TI ADC circuitry and generates corrected output signals using weight values to correct time skew. The correction circuitry includes a derivative filter which removes frequency dependency between the weight values and input signals to the TI ADC circuitry. Weight updating circuitry receives the corrected output signals and generates updated weight values for the correction circuitry. The weight updating circuitry includes a notch filter which suppresses spectral content in the corrected output signals to cancel spurious correlations in the weight updating process.

Abstract: There is described a method of operating an NFC device, the method comprising: determining a resonance frequency of a matching network of the NFC device; modulating, by a modulator, a carrier signal received from an external reader, resulting in a modulated carrier signal; controlling, using a controller, a transmission of the modulated carrier signal to the external reader; and transmitting, by a transmitter driver, said modulated carrier signal, said transmitter driver having at least one configurable setting that influences a damping behavior of the transmitted modulated carrier signal, wherein, during a modulation phase of the NFC device, the controller selects and applies the at least one configurable setting based on the determined resonance frequency such that a clock synchronization window is widened. Furthermore, a corresponding NFC device is described.

Abstract: A device includes a first radio controller configured to communicate using a first protocol, and a pseudo random number generator configured to generate a pseudo random output value based on an input data value. The device includes a processor configured to determine a preamble code based on an output of the pseudo random number generator, and process a data packet received using the first radio controller using the preamble code to generate a processed data packet.

Abstract: A semiconductor device includes a semiconductor substrate, a collector region formed within the semiconductor substrate in a first semiconductor region having an upper surface and a collector sidewall, a base region disposed over the collector region, a seed region formed over the semiconductor substrate and coupled to the semiconductor substrate outside the base region, an extrinsic base region having an upper surface and formed over the seed region and electrically coupled to the base region, and an emitter region formed over the base region.

Abstract: In accordance with a first aspect of the present disclosure, an ultra-wideband (UWB) receiver is provided, comprising: an attack mitigation unit configured to mitigate one or more attacks on a correlation function; a correlation unit configured to perform the correlation function by correlating an input signal received by the UWB receiver with a predefined sequence and to generate a correlation output based on correlating said input signal with the predefined sequence; and a first path detection unit configured to receive the correlation output and to detect a first path by evaluating the correlator output during a correlation window, said correlation window being a predefined period of time. In accordance with a second aspect of the present disclosure, a corresponding method of operating a UWB receiver is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.

Abstract: An adaptive noise classifier and a controller for controlling various noise cancellation systems of a vehicle are provided. The adaptive noise classifier determines a first acoustic state of the vehicle based on audio signals generated by various audio-capturing devices of the vehicle. The controller receives status data indicative of one or more functional attributes of the vehicle. Based on the status data and the first acoustic state, the controller determines a second acoustic state. The second acoustic state is an updated version of the first acoustic state. Based on the second acoustic state, the controller controls an operational state of each noise cancellation system of the vehicle.

Abstract: The present disclosure relates to an oscillator, such as a Digitally Controlled Oscillator (DCO), having first capacitor banks coupled to a first path and a second path, the first path connecting a first node to a first output node, and the second path connecting a second node to a second output node, and second capacitor banks coupled to a third path and a fourth path, the third path being connected to the first node, the fourth path being connected to the second node, the first and second paths being separate from the third and fourth paths, and the second capacitor banks including at least one modulation capacitor bank.

Abstract: A frequency beam-steered leaky wave antenna suitable for integration in a substrate such as a printed circuit board includes a waveguide formed from a first electrically-conductive surface and a second electrically conductive surfaces forming upper and lower surfaces of the waveguide and electrically-conductive vias form first and second sidewalls disposed between the upper and lower surfaces along a length of the waveguide. The waveguide has slotted openings distributed along the upper surface and a width of the waveguide is defined by a distance between the two sidewalls that varies along the length of the waveguide. A portion of radiofrequency energy travelling along a length of the waveguide is radiated away from the waveguide through the slotted openings. Performance characteristics of the antenna such as its directivity and operational bandwidth can be tuned by adjusting the geometry of the slotted openings and positioning of the vias.

Abstract: The disclosure relates to supporting multiple logical interfaces over a single physical interface, in particular relating to supporting multiple profiles on eSIMs/eUICCs.

Abstract: A chopper circuit (100) for a multipath chopper amplifier (201) is described. The chopper circuit (100) comprises a first chopper device (110) in a first circuit path (111), wherein the first chopper device (110) is configured to be controlled by a first clock signal (315), which has a first frequency; and a second chopper device (120) in a second circuit path (121), parallel to the first circuit path (111), wherein the second chopper device (120) is configured to be controlled by a second clock signal (325), which has a second frequency, wherein the first frequency is greater than the second frequency. Furthermore, a corresponding method of chopping an input signal (102) is described.

Abstract: Various aspects of the disclosure are directed to the communication and processing of radar signals. As may be implemented in accordance with one or more embodiments characterized herein, receiver-generated phase lag is compensated by phase smoothing and pre-distorting radar signals. The radar signals are transmitted and reflections of those signals from various objects are processed by aligning respective waveforms in the reflections using group delay filtering, and differentiating the aligned waveforms via decoding. The phase lag compensation carried applied to the signals prior to transmission facilitates the differentiation (e.g., by facilitating alignment prior to decoding).

Abstract: A modulator circuit may include an integrator circuit and a gain compensation circuit. The integrator circuit may include a first amplifier including an input to receive a signal and an output to provide an inverted signal and a capacitor including a first terminal coupled to the input and a second terminal coupled to the output. The gain compensation circuit may include a second inverter amplifier including a gain input coupled to the output of the first amplifier and including a gain output; a first resistor including a first terminal coupled to the gain output and including a second terminal; and a second capacitor including a first terminal coupled to the second terminal of the first resistor and including a second terminal coupled to the gain input. The integrator circuit has a finite DC gain and the gain compensation circuit is configured to compensate for the finite DC gain.

Abstract: In accordance with an aspect of the present disclosure, a communication system is provided, comprising: a first ultra-wideband (UWB) transmitter configured to be coupled to a first antenna; a second UWB transmitter configured to be coupled to a second antenna; a controller configured to cause the first UWB transmitter to transmit a first packet to an external communication device, wherein the first packet contains a predefined code; wherein the controller is further configured to cause the second UWB transmitter to transmit a second packet to the external communication device, wherein the second packet contains a cyclically shifted version of said predefined code.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes affixing a spacer structure to a bottom side of a plurality of leads of a leadframe. A semiconductor die is attached to a top side of a die pad of the leadframe. The semiconductor die, the leadframe, and the spacer structure are encapsulated with an encapsulant. Portions of the spacer structure and portions of the leads of the plurality of leads are exposed at a bottom side of the encapsulant.

Abstract: A processor and methods of detecting a corrupted instruction stream within a processor include executing, by the processor, a program including a plurality of basic blocks, each of which includes a sequence of instructions to be executed by the processor without branching. The method includes implicitly initializing a first cyclic-redundancy-check (CRC) generator based on a first portion of an address of a first instruction in a first basic block and a second CRC generator based on a second portion of the address of the first instruction, generating, by the first CRC generator, a first CRC output according to a first polynomial and, by the second CRC generator, a second CRC output according to a second polynomial, and when an end of the first basic block is reached without encountering an instruction to transfer control from a first function to a second function, selectively deferring a CRC check operation.

Abstract: An electrostatic discharge circuit for a semiconductor die includes a plurality of GGNMOS transistors coupled between a first rail and a second rail of the semiconductor die. Each GGNMOS transistor includes a body contact that is coupled to a trigger rail through a ballast circuit and is coupled to the second rail. During the detection of an ESD event of a sufficient severity, the trigger rail is placed in an asserted condition to make the GGNMOS transistors conductive to discharge ESD current from the first rail to the second rail.

Abstract: A MIMO radar apparatus includes M simultaneously transmitting radar transmitters, N radar receivers, and control circuitry coupled thereto. Positions of the M transmitters and N receivers define M×N virtual transceiver positions; at least one virtual transceiver position coincides with another. The control circuitry transmits simultaneously radar output signals via the transmitters, receives radar return signals arising from the output signals via the receivers, and generates N corresponding electronic receiver signals, and can further generate M×N virtual transceiver signals and estimate angular positions of backscattering/backreflecting objects. Comparing signal characteristics arising from the same virtual transceiver position but from different corresponding transmitter/receiver pairs can enable identification of low-confidence estimated angular positions arising from out-of-field-of-view or multipath propagation of radar signals.

Abstract: In accordance with a first aspect of the present disclosure, a voltage regulator is provided, comprising: a core and an output stage configured to be coupled to the core, wherein said output stage comprises a set of output stage units; a switch unit comprising a plurality of controllable switches, wherein said controllable switches are configured to couple subsets of the set of output stage units to the core. In accordance with a second aspect of the present disclosure, a corresponding method of configuring a voltage regulator is conceived.

Abstract: A method of operation for a side-channel leakage engine includes initializing a plurality of copy registers with a respective initial value. A respective copied value is copied from a leakage value circuit to at least one of the copy registers, wherein the leakage value circuit comprises a data register comprising a leakage value and each of the copy registers comprises a respective plurality of bits comprising a same number of bits as the data register. An observable characteristic of the side-channel leakage engine is generated, wherein the observable characteristic is proportional to a number of bit transitions of the respective plurality of bits of each of the copy registers, transitioning from the respective initial value to the respective copied value.

Abstract: A method is provided for visualizing a classification prediction by a machine learning model of a first image. A second image having similar features to the first image is chosen from a training data set used to train the machine learning model. A localization map is generated to show a location of similar features between the first and second images. The localization map includes a gradient of features toward a particular class to determine a relevance of the features determined to be mutually similar with respect to the particular class. The features not mutually similar with respect to the particular class are excluded from the localization map. The localization map is overlaid with the second image. A visualization of mutual class important features between the first and second images is generated from the overlay. The method may be implemented in a computer program having instructions executable by a processor.