Abstract: A controller for a power converter includes a generator module which generates a sequence of pulses each having a width defined by a rise moment and fall moment stored in respective RM and FM registers. The sequence of pulses have a repetition rate that is modulated by a repetition period value stored in a RP register. A memory of the controller has tables of rise moment values, fall moment values and repetition period values configured to be written into the RM, FM and RP registers respectively. A direct memory access (DMA) module of the controller is configured to write rise moment, fall moment, and repetition period values from the respective memory table into the RM, FM, and RP registers respectively, in response to a DMA trigger. A core coupled to the DMA module is configured to write the rise moment, fall moment, and repetition period values into the memory tables.

Abstract: One example discloses a security device, including: a bulk security capacitance, including a first endpoint and a second endpoint, and having, a first layer including a first set of conductive elements, the first endpoint, and the second endpoint; and a second layer including a second set of conductive elements; wherein the first set of conductive elements and the second set of conductive elements together form at least two bulk capacitors in series; wherein the first and second layers are separated by a distance; and wherein the first and second endpoints are configured to be coupled to a tamper detection circuit configured to detect a change in the bulk security capacitance.

Abstract: Digitally controllable elements capable of influencing operation of a power amplifier module are coupled in parallel to a serial data interface. Each digitally controllable element includes address control logic that decodes an address presented on the serial data interface as well as a device specific ID. In response to the decoding, physical registers in different digitally controllable elements are written in an interleaved order according to an interleaved register address map. Banks of registers within the digitally controllable elements may be select to influence or modify operation of the power amplifier module.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a radiating element structure and a semiconductor die. The radiating element structure includes a non-conductive substrate, a radiating element formed at a top side of the non-conductive substrate, and a conductive ring formed at the top side of the non-conductive substrate substantially surrounding the radiating element. The semiconductor die is interconnected with the radiating element by way of a conductive trace. An encapsulant encapsulates at least a portion of the radiating element structure. A top surface of the conductive ring exposed at a top surface of the encapsulant. A waveguide interface material is applied on at least a portion of the top surface of the encapsulant.

Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die on a carrier substrate and placing a sacrificial blank on the carrier substrate with a routing structure attached to the sacrificial blank. At least a portion of the semiconductor die, sacrificial blank, and routing structure are encapsulated with an encapsulant. The carrier substrate is separated from a first side of the encapsulated semiconductor die, sacrificial blank, and routing structure to expose a surface of the sacrificial blank. The sacrificial blank is etched to form a cavity in the encapsulant and expose a portion of the routing structure exposed through the cavity.

Abstract: Provided is a contactless connector that includes an antenna system and a wireless transceiver coupled to the antenna system and configured to simultaneously transmit a transmission signal and receive a received signal through the antenna system. The wireless transceiver includes a transformer, a wide-band phase shifter and a combiner. The transformer has a primary coil with a center tap to which the transmission signal is coupled and a first end that is coupled to the antenna system. The transmission signal also is coupled to an input of the wide-band phase shifter. The transformer also has a secondary coil, an output of the secondary coil is coupled to a first input of the combiner, an output of the wide-band phase shifter is coupled to a second input of a combiner, and an output of the combiner provides a self-interference-canceled version of the received signal.

Abstract: A time-synchronization apparatus and/or method involves identifying a frequency offset by implementing a frequency-offset-acquisition process which includes counting cycles of a local clock signal within a period of a reference pulse train. A phase offset of the local clock signal is determined, a residual frequency error is generated based on the phase offset, and at least one timer-adjustment signal that is based on the frequency offset and the residual frequency error is provided.

Abstract: A method to retrieve transaction address resulting in PCIe completion timeout includes monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a Completion Timeout (CTO) transmitted therefrom. A Master Identification (ID) of a Master and a transaction address of a transaction are stored in a configuration space, in response to detecting the CTO, wherein the transaction originates from the Master and the CTO is signaled in response to the transaction. The CTO is responded to with the Master identified by the Master ID in the configuration space.

Abstract: A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

Abstract: A communication system, including: a first modulator configured to modulate a first periodic signal with a first frequency based upon an input signal; a second modulator configured to modulate a second periodic signal with a second frequency based upon the input signal; an isolated differential channel including isolation capacitors with a first line connected to the first modulator and a second line connected to the second modulator; a mixer configured to mix signals received from the first line and the second line of the differential channel and to produce a mixer output signal; a bandpass filter connected to the mixer configured to filter the mixer output signal; an envelope detector configured to detect an envelope of the filtered mixer output signal; and a detector configured to detect a data signal in the envelope of the filtered mixer output signal and to produce an output signal.

Abstract: Test coverage for a circuit design may be determined by obtaining node testability data and physical location data for each node of a plurality of nodes in the circuit design. A determination is made that one or more low test coverage areas within the circuit design include untested nodes based on the node testability data and the physical location data of each node of the plurality of nodes. Test coverage data is generated for the circuit design including at least an identification of the one or more low test coverage areas.

Abstract: A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.

Abstract: Oscillator circuitry and methods of operation thereof are provided in which the oscillator circuitry includes at least a first oscillator, a second oscillator, and a lock detector. The first oscillator is configured to generate a first clock signal. The second oscillator is configured to generate a second clock signal. The lock detector is configured to detect a stable phase lock between the first clock signal and the second clock signal and to switch an output of the oscillator circuitry from the first clock signal to the second clock signal in response to detecting the stable phase lock.

Abstract: A bandgap reference circuit includes a first current generator having first and second bipolar transistors for generating a first current that varies proportionally as a function of temperature. A second current generator includes a field effect transistor for generating a second current that varies inversely as a function of temperature. A trimming circuit includes a third bipolar transistor sized to match the first bipolar transistor, a third current generator having a second field effect transistor coupled to a collector and base of the third bipolar transistor to generate a third current based on a base current of the third bipolar transistor, and a trim control circuit configured to modify the second current by adding the third current to or subtracting the third current from the second current based on a trim control signal. A bandgap reference current is generated by summing the first current and the modified second current.

Abstract: A system includes a reference field effect transistor (FET), wherein the reference FET is a depletion mode transistor, and a bias control circuit. The bias control circuit includes a voltage sensor connected to a drain terminal of the reference FET. The voltage sensor is configured to measure a voltage at the drain terminal of the reference FET as a measured voltage, determine a voltage difference between a reference voltage and the measured voltage, and output the voltage difference at a voltage sensor output terminal. The system includes a translation circuit connected the voltage sensor output terminal. The translation circuit is configured to convert the voltage difference into a negative gate bias voltage, and apply the negative gate bias voltage to a gate terminal of the reference FET.

Abstract: Systems and methods for controlled application of hysteresis in crystal oscillator circuits are discussed. In various embodiments, an Integrated Circuit (IC) may include: an inverter comparator coupled to a crystal oscillator, where the inverter comparator is configured to: (i) receive an input of the crystal oscillator, and (ii) output a clock signal; and a hysteresis control circuit coupled to the inverter comparator, wherein the inverter comparator is configured to: (i) start up with hysteresis disabled, and (ii) enable hysteresis in response to a hysteresis enable signal provided by the hysteresis control circuit.

Abstract: Systems and methods for managing asynchronous resets in an SoC have been described. In an illustrative, non-limiting embodiment, a reset generation circuit in an SoC, may include a first reset generation circuit configured to enable a first reset signal based, at least in part, upon a clock signal and an indication to reset. The reset generation circuit may also include a second reset generation circuit coupled to the first reset generation circuit, in which the second reset generation circuit is configured to enable a second reset signal after the first reset signal is enabled. The first reset signal and the second reset signal are both provided to a component of the SoC.

Abstract: A back-end-of-line integrated circuit interconnect device is formed on an integrated circuit structure having a first dielectric layer formed over a first conductive contact layer by forming an interconnect opening in the first dielectric layer which exposes at least a portion of the first conductive contact layer, filling the interconnect opening in the first dielectric layer with one or more polyimide layers in contact the first conductive contact layer; and applying a laser light source to directly convert the one or more polyimide layers to form a graphene interconnect structure in the first dielectric layer which is directly, electrically connected to the first conductive contact layer.

Abstract: A back-end-of-line integrated circuit is formed on an integrated circuit structure having one or more polymer interlayer dielectric (ILD) layers formed over a first conductive wiring line layer by selectively processing an exposed portion of the one or more polymer ILD layers with application irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer.

Abstract: A semiconductor device and fabrication method are described for integrating a nanosheet transistor with a multimodal transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source/drain structures in an MMT region that are laterally spaced apart from one another and positioned below an MMT semiconductor channel layer before forming a transistor stack of alternating Si and SiGe layers in an FET region which are selectively processed to form gate electrode openings so that a first ALD oxide and metal layer are patterned and etched to form gate electrodes in the transistor stack and to form a channel control gate electrode over the MMT semiconductor channel layer, and so that a second oxide and conductive layer are patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.