Patents Assigned to NXP USA, INC.
  • Publication number: 20190181860
    Abstract: A touch sensitive capacitive keypad system (100) is provided with an analog-to-digital converter, a keypad sensing electrode (114) coupled to measure capacitance voltages using a configurable electrode scan rate, and a controller (120) configured to provide scan-rate independent capacitance voltage measurements from the keypad sensing electrode to the analog-to-digital converter when there is a change in the configurable electrode scan rate by repetitively sampling a capacitance voltage measurements (e.g., 524a-f) from the keypad sensing electrode over a plurality of sequential electrode scan cycles and then discarding a predetermined number of the capacitance voltage measurements (e.g., 524a-b) to generate the scan-rate independent capacitance voltage measurements (e.g., 524c-f) that are provided to the analog-to-digital converter.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: NXP USA, Inc.
    Inventor: Petr Cholasta
  • Publication number: 20190179629
    Abstract: A software update architecture, system, apparatus, and methodology are provided for performing block-based swapping of OTA software stored as a plurality of compressed blocks in a first, smaller NVM with the system software stored as a plurality of decompressed blocks in a second, larger NVM by using a first decompressor circuit and first scratch memory to sequentially decompress each compressed code block of OTA software for storage in decompressed form as updated system software in the second, larger NVM while using a first compressor circuit and second scratch memory to sequentially compress each decompressed code block of system software for storage in compressed form as backup system software in the first, smaller NVM.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: NXP USA, Inc.
    Inventors: Anirban Roy, Anis M. Jarrar, Frank K. Baker, JR.
  • Publication number: 20190178938
    Abstract: An on-chip built-in self-test (BIST) circuit (10) uses a controller (16), analog-to-digital converter (ADC) (15), and digital-to-analog converter (DAC) (12) to sense voltage and/or temperature measures at predetermined circuit locations (19), to detect one or more idle states for an analog block during normal operation, to initiate a built-in self-test of the analog block during the idle state(s) by sending input test signals over a first bus (13) to the analog block, and to process analog test signals received over a second bus (14) from the analog block to generate digital built-in self-test results for the analog block so that the performance analyzer can analyze the digital built-in self-test results in combination with any voltage and/or temperature measurements to evaluate selected performance measures for the analog block against one or more performance criteria.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: NXP USA, Inc.
    Inventors: Xiankun Jin, Douglas A. Garrity
  • Patent number: 10319689
    Abstract: Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (RF) signal; a printed circuit board (PCB) attached to a front side of the package substrate, where the PCB includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang
  • Patent number: 10320185
    Abstract: An integrated circuit for protecting against transient electrical stress events includes a rail clamp device, and a trigger circuit including a resistive-capacitive (RC) filter, a drive circuit including a first inverter stage receiving an input signal from the RC filter, the drive circuit is configured to enable the rail clamp device during a transient electrical stress event, and a stress event detection circuit coupled to the RC filter. The drive circuit includes a configurable activation voltage which is controlled by the stress event detection circuit, wherein the activation voltage is reduced when the transient electrical stress event is detected.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Robert Matthew Mertens, Alexander Paul Gerdemann, Michael A. Stockinger
  • Patent number: 10318447
    Abstract: A Universal SPI Interface is provided that is compatible, without the need for additional interface logic or software, with the SPI bus, existing DSA and other serial busses similar to (but not directly compatible with) the SPI bus, and parallel busses requiring compatibility with 74xx 164-type signaling. In an additional aspect, a reduced-pincount Universal SPI Interface is provided that provides the same universal interface, but using fewer external output pins. The Universal SPI Interface includes multiple latches, buffers, and in an alternative embodiment, a multiplexer, configured together such that a Universal SPI Interface is provided that can be readily reconfigured using only input signals to provide compatibility across multiple bus interfaces.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Nicholas J. Spence, Jason R. Fender, Michael L. Fraser
  • Patent number: 10319660
    Abstract: A heat transportation mechanism that is thermally conductive, but not electrically conductive, is provided so as to permit transportation of heat generated by a semiconductor device die to the exterior of a semiconductor device package. Embodiments can use a thermally conductive polymer structure, added to the package mold compound, to transport heat through the mold compound. The thermally conductive polymer structure can be fixed to the semiconductor device die prior to molding or can be included in an overmolding compound slug prior to performing the overmolding process. Flexibility of placement of the thermally conductive polymer structure is provided by using dielectric compounds.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: June 11, 2019
    Assignee: NXP USA, INC.
    Inventor: Christopher W. Argento
  • Patent number: 10317921
    Abstract: A power supply is disclosed. The power supply includes a first switch and a second switch. The gate of the first switch is coupled to the gate of the second switch. The power supply further includes a cutoff switch coupled between the first switch and an input voltage port. A comparator is included for comparing a voltage at a feedback port with a fixed reference voltage. The comparator opens the cutoff switch when the voltage at the feedback port is lower than the fixed reference voltage.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventor: Xianghua Shen
  • Patent number: 10319815
    Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Xiaowei Ren, Robert P. Davidson, Mark A. DeTar
  • Patent number: 10320387
    Abstract: An integrated circuit includes a digital logic circuit having a first transistor and a second transistor, a replica circuit having a first transistor and a second transistor which replicate the first transistor and second transistor of the digital logic circuit, and a storage circuit configured to store a static state indicator. The circuit also includes a comparison circuit configured to compare threshold voltages of the first and second transistor of the replica circuit, and having an output coupled to provide the static state indicator to the storage circuit, and a selection circuit configured to provide the state indicator to an input of the digital logic circuit and an input of the replica circuit during a lower power mode and to provide a run mode signal instead of the state indicator to the input of the digital logic signal and the input of the replica circuit during a high power mode.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Ivan Carlos Ribeiro Do Nascimento, Armando Gomes Da Silva, Jr.
  • Patent number: 10318466
    Abstract: A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalize the at least one outstanding interconnect transaction with the interconnect component.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Robert Krutsch, Christian Tuschen
  • Patent number: 10320562
    Abstract: A key generator including a low-power key adjust circuit, and a high-power key adjust circuit. The low-power key adjust circuit including a storage location to store an original key, a shifter to shift the original key by a number of steps to shift to create a first key, and an output to provide the first key. The high-power key adjust circuit including an input coupled to the output of the low-power key adjust circuit to receive the first key, a scrambler to scramble the first key to create a scrambled key, and select circuitry to select either the first key or the scrambled key to output from the high-power key adjust circuit based on a bit in a configuration register.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Eran Glickman, Ron M. Bar, Omer Sharon
  • Patent number: 10312977
    Abstract: A receiver decodes received data streams based on a subset of candidate decoding constellation points. A first stage of a decoder of the receiver selects a subset of candidate decoding constellation points by identifying a decoded value for an initial data stream of the set of data streams. A second stage then applies MMSE error detection to each of the constellation points in the selected subset, and calculates an error metric based on the MMSE error detection results. The decoder selects the constellation points having the lowest error metrics, and uses the selected constellation points as an initial set of points for decoding the next data stream to be decoded.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventors: Marius Octavian Arvinte, Wim Joseph Rouwet
  • Patent number: 10312929
    Abstract: The embodiments described herein provide analog-to-digital converters and methods that can reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals while still providing the ability to perform an accurate analog-to-digital conversion. In general, the embodiments described herein reduce the likelihood of excessive voltage drop during the conversion of weakly driven signals by pre-charging the sampling capacitor used in the conversion. For example, the embodiments can apply the buffered input signal apply to the sampling capacitor for a first sampling cycle to pre-charge the sampling capacitor, and then directly apply the unbuffered input signal to the sampling capacitor for a second sampling cycle to final-charge the sampling capacitor. With the sampling capacitor charged using the two stage charging, a digital output corresponding to the charge of the sampling capacitor is generated.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventors: Kumar Abhishek, Srikanth Jagannathan, Shanaka Pradeep Yapa Appuhamillage Don
  • Patent number: 10312905
    Abstract: The invention provides a bond wire arrangement comprising a signal bond wire (1) for operably connecting a first electronic device (6) to a second electronic device (8), and a control bond wire (2) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire (1), and having a first end (11) coupled to ground, and a second end (12) coupled to ground via a resistive element (14). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventor: Youri Volokhine
  • Patent number: 10311241
    Abstract: A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventors: Joachim Fader, Robert Krutsch, Dirk Wendel
  • Patent number: 10310531
    Abstract: A current regulator circuit to improve electromagnetic compatibility performance operation of an IC device includes an input to receive a regulated voltage signal, an output to provide an output voltage at a desired voltage level, the output voltage exhibiting noise from a load, a first field effect transistor FET including a first source electrode coupled to the input, a first drain electrode coupled to the output, and a first gate electrode, a voltage clamp circuit coupled to the output, the voltage clamp circuit configured to conduct a varying current based upon the noise, a constant current source to provide a constant current, and a second FET including a second source electrode coupled to the output, a second drain electrode coupled to the constant current source and to the first gate electrode, and a second gate electrode coupled to the voltage clamp circuit to mirror the varying current in the second FET.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventors: Pascal Kamel Abouda, Bertrand Vrignon
  • Patent number: 10312368
    Abstract: Semiconductor devices include a semiconductor substrate containing a source region and a drain region, a gate structure supported by the semiconductor substrate between the source region and the drain region, a composite drift region in the semiconductor substrate, the composite drift region extending laterally from the drain region to at least an edge of the gate structure, the composite drift region including dopant having a first conductivity type, wherein at least a portion of the dopant is buried beneath the drain region at a depth exceeding an ion implantation range, and a well region in the semiconductor substrate. The well region has a second conductivity type and is configured to form a channel therein under the gate structure during operation. Methods for the fabrication of semiconductor devices are described.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventors: Philippe Renaud, Zihao M. Gao
  • Patent number: 10312230
    Abstract: Electrostatic discharge (ESD) protection circuitry in an integrated circuit is provided. The protection circuitry includes a trigger circuit coupled between a first power supply bus and a second power supply bus. A delay circuit is coupled to receive an output signal from the trigger circuit. The delay circuit includes a first inverter coupled to the input of the delay circuit and a feedback transistor having a control terminal coupled to the output of the delay circuit, a first current electrode coupled to the first power supply bus, and a second current electrode coupled to the output of the first inverter. A clamp driver circuit is coupled to the output of the delay circuit.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: June 4, 2019
    Assignee: NXP USA, Inc.
    Inventor: Cynthia A. Torres
  • Patent number: 10302514
    Abstract: A pressure sensor includes a diaphragm suspended across a cavity in a substrate. A first group of piezoresistors is provided in the diaphragm proximate a first outer edge of the diaphragm, the piezoresistors of the first group being coupled to one another to form a first Wheatstone bridge. A second group of piezoresistors is provided in the diaphragm proximate a second outer edge of the diaphragm, the piezoresistors of the second group being coupled to one another to form a second Wheatstone bridge. The first and second Wheatstone bridges exhibit mirror symmetry relative to one another. Output signals from each of the first and second Wheatstone bridges are processed at respective first and second differential amplifiers. The output signals from each of the first and second differential amplifiers are processed at a third differential amplifier to produce a pressure output signal with enhanced sensitivity and reduced impact from process variation.
    Type: Grant
    Filed: December 18, 2016
    Date of Patent: May 28, 2019
    Assignee: NXP USA, Inc.
    Inventor: Lianjun Liu