Abstract: One example discloses a first-device: wherein the first-device is configured to be coupled to a second-device over an IEEE 802.11 communications link; and wherein the first-device is configured to, store a current setup between the first-device and the second-device; identify a unique identifier of the second-device; transmit a request frame to a third-device; wherein at least one of the second-device and third-device is a multi-link-device (MLD); wherein the request frame is configured to request an association with the third-device and includes the unique identifier of the second-device; receive a response frame from the third-device; and wherein the response frame includes an indication that request was successful.

Abstract: A modem for a non-standalone network includes a 5G-NR modem and an E-UTRA modem. The 5G-NR modem includes a cell search module which determines first timing information. The first timing information includes first times indicative of the times of receipt of one or more first radio frames from a first 5G-NR base station measured relative to a network time. The 5G-NR modem also provides for the sending of system frame timing difference (SFTD) information for the first base station to a network controller by sending the first timing information to the E-UTRA modem. The E-UTRA modem then determines and forwards the SFTD information using the first timing information and second timing information. The second timing information is determined by the E-UTRA modem and includes second times indicative of the times of receipt of one or more second radio frames from a second E-UTRA base station.

Abstract: The disclosure relates to a system for transmitting Protocol data units (PDUs). Example embodiments include a system comprises a radio link control (RLC) layer for storing a RLC PDU list of RLC Protocol Data Units (PDUs) received from a ProtocolData Convergence Protocol (PDCP) layer. The control layer comprises a transmission block for transmission to a Media Access Layer (MAC) layer in a transmission event, wherein the transmission block is populated with a subset of PDUs in the RLC PDU list. When the transmission block is near a storage limit, the system scans the RLC PDU list for a PDU that best fits a remaining grant of the transmission block to complete population of the transmission block. The control layer further comprises a priority list for storing PDUs of the RLC PDU list scanned by the system that were greater in size than the remaining grant.

Abstract: An access point device operable in a wireless network detects multi-band capability of a wireless client based on a probe request received from the wireless client on the non-preferred communication band. The multi-band capability is detected based on a set of parameters included in the received probe request. When the wireless client is detected to have the multi-band capability, the access point device blocks the attempt of the first wireless client to associate on the non-preferred communication band. The access point device allows the wireless client to associate on one of the non-preferred communication band and a preferred communication band based on a count of probe requests received by the access point device from the wireless client on the non-preferred communication band. Upon association on the non-preferred communication band, the access point device steers the associated wireless client to the preferred communication band.

Abstract: A wireless network includes a networking device and various stations. The networking device determines an available bandwidth of each station of the wireless network. Further, the networking device assigns a bandwidth and at least one spatial stream to each station. The bandwidth assigned to each station is less than or equal to the available bandwidth of the corresponding station. Further, the bandwidth assigned to one station is different from and partially overlaps with the bandwidth assigned to another station. Similarly, the spatial stream assigned to one station is different from the spatial stream assigned to another station. The networking device generates a data packet indicative of the bandwidth and the spatial stream assigned to each station of the wireless network, and transmits the data packet to each station to enable multi-user multiple-input-multiple-output (MU-MIMO) communication between the networking device and the stations.

Abstract: A semiconductor device comprises a substrate including a set of interconnect pads, a die mounted on the substrate, wherein the die includes circuitry that cannot withstand typical lead-free (Pb-free) solder reflow temperature during reflow process, and a reinforcing interposer including a first set of interconnect pads and a second set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads on the substrate to a corresponding one of the first set of interconnect pads on the reinforcing interposer. A printed circuit board includes a set of interconnect pads. Low temperature solder material connects one of the set of interconnect pads of the printed circuit board to a corresponding one of the second set of interconnect pads of the reinforcing interposer. The low temperature solder material has a reflow temperature below typical Pb-free solder material.

Abstract: The processor system includes a processor coupled to a memory having a plurality of memory banks and a region configurable as a heap region. At least one memory bank is allocated to the heap region dependent on a predetermined memory size required for execution of at least one cryptographic operation. At least one further memory bank is allocated to the heap region. The processor system may switch between first and second operating states. The first operating state has a lower power consumption than the second operating state. The processor system switches between a first and second operating mode by setting at least one memory bank and at least one further memory bank to an active state. The processor system switches between the second and first operating mode by setting at least one memory bank to a retention state and the at least one further memory bank to a power-down state.

Abstract: Stable switching is disclosed for a power factor correction boost converter using an input voltage and an output voltage. In one example, a boost converter control system includes a gate driver coupled to a switch of a boost converter to generate a drive signal to control switching of the switch, wherein a period of the drive signal is adjusted using a current adjustment signal. A current control loop is coupled to the gate driver to receive a sensed input current from the boost converter and a desired input current and to generate the current adjustment signal to the gate driver. A current limiter is coupled to the gate driver and the current control loop to determine a duty cycle of the switch, to determine a maximum input current in response to the duty cycle, and to restrict the desired input current to below the maximum input current.

Abstract: A method and apparatus are described for controlling the phase of an interleaved boost converter using cycle ring time. In an embodiment, a cycle controller generates a first drive signal to control switching of a first converter and a second drive signal to control switching of a second converter, the controller receives a first cycle signal from the first converter and a second cycle signal from the second converter, wherein the first cycle signal and the second cycle signal have a power phase time and a ringing phase time. The cycle controller determines a master ringing phase time of the first cycle signal and applies the master ringing phase time to the second cycle signal to determine a slave ringing phase time. The cycle controller generates the second drive signal in accordance with the slave ringing phase time.

Abstract: Embodiments of a circuit, system, and method are disclosed. In an embodiment, a circuit includes first and second microstrip transmission lines. The first and second microstrip transmission lines include linearly arranged conductive strips on the circuit and a slotline formation extends between the first microstrip transmission line and the second microstrip transmission line so that the slotline formation is configured to electromagnetically couple the first microstrip transmission line to the second microstrip transmission line during operation of the circuit. In addition, the circuit includes at least one controllable capacitance circuit electrically connected to at least one of the first microstrip transmission line and the second microstrip transmission line, where a magnitude of a capacitance value of the at least one controllable capacitance circuit (e.g., including a barium strontium titanate (BST) capacitor) is controllable (e.g.

Abstract: A Remap Address Space Controller controls access to an address space by selectively remapping a physical address of a transaction received from a controller to form a remapped physical address according to a current execution context of the controller. The selective remapping is based on a determination of whether the current execution context of the controller allows the transaction to access the address space. Remap Address Space Controller selectively provides the transaction with the remapped physical address to a memory bus based on the determination of whether the current execution context of the controller allows the transaction to access the address space.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a difference co-array virtual aperture by using a radar control processing unit to coherently combine virtual array apertures from multiple small aperture radar devices to construct a sparse MIMO virtual array aperture and to construct an extended difference co-array virtual array aperture that is larger than the MIMO virtual array aperture by using an FFT hardware accelerator to perform spectral-domain auto-correlation based processing of the sparse MIMO virtual array aperture to fill in holes in the sparse MIMO virtual array aperture and to suppress spurious sidelobes caused by holes in the sparse MIMO virtual array aperture.

Abstract: A controller for a half-bridge power circuit includes a measurement circuit, a controller circuit, a high-side delay circuit, and a low-side delay circuit. The measurement circuit connects to the half-bridge node, measures the half-bridge voltage, and generates a multi-bit status signal indicative of the measured half-bridge voltage. The controller circuit connects to the measurement circuit, and receives the status signal therefrom. The controller circuit generates at least a delay control signal based on the status signal. The high-side delay circuit connects to the controller circuit to receive the delay control signal. The high-side delay circuit provides a high-side control signal in response to the delay control signal, to switch on/off the high-side switch. The low-side delay circuit connects to the controller circuit to receive the delay control signal. The low-side delay circuit provides a low-side control signal in response to the delay control signal, to switch on/off the low-side switch.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves encoding bits in a Physical Layer Protocol Data Unit (PPDU) using a basic bandwidth that is smaller than a signal bandwidth, wherein the bits are duplicated within the PPDU, and transmitting the PPDU with duplicated bits in accordance with a power spectrum density (PSD) limit.

Abstract: A wireless communication system include user equipment which includes a receive antenna for receiving mmWave signals from a base station transmitter. The system also includes a barrier configured to focus electromagnetic radiation carrying the mmWave signals onto the receive antenna of the user equipment.

Abstract: A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip (SoC) resources using virtual addresses; a control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a runtime virtualization isolation control data stream for controlling access to the SoC resources by identifying at least a first SoC resource that the first execution domain is allowed to access; and an access control circuit connected between the first execution domain and the SoC resources and configured to provide, in response to the runtime virtualization isolation control data stream, a dynamic runtime virtualization isolation barrier which maps a virtual address for the first SoC resource to a physical address for the first SoC resource.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts n partitions by accessing, for each partition, one or more SoC resources; a control point processor that generates control data with n JTAG debug enable signals corresponding to the n partitions for controlling access to the SoC resources by identifying at least a first SoC resource that each partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which allows access by the JTAG debugging tool to only a specified partition running on the execution domain which has a JTAG debug enable signal set to a first active value and prevents access to the other n-1 partitions running on the execution domain, and for the partition under debug (debug signal set to a first active value), the dynamic runtime isolat

Abstract: A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip resources; a first control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a first runtime isolation control data stream for controlling access to the one or more system-on-chip resources by the first execution domain; and an access control circuit connected between the first execution domain processor and the one or more system-on-chip resources and configured to provide a dynamic runtime isolation barrier in response to the first runtime isolation control data stream, thereby controlling access to the one or more system-on-chip resources by the first execution domain.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain; a control point processor that is physically and programmatically independent from the execution domain processor and configured to generate control data for controlling access by the execution domain to one or more SoC resources by identifying at least a first SoC resource that the execution domain is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and including a programmable front end which is connected to receive the control data from the control point processor, and a signals-based back end which is configured to provide a dynamic runtime isolation barrier in response to the control data, thereby controlling access to the one or more system-on-chip resources by the execution domain.