Abstract: A power supply circuit and a method for operating a power supply circuit involves selecting a normal operational mode or a pass-through operational mode for a switched mode power supply, in the normal operational mode, converting an input voltage of a power supply circuit to an intermediate voltage using a switching regulator of the switched mode power supply, in the pass-through operational mode, disabling the switching regulator such that the input voltage of the power supply circuit is unchanged by the switching regulator and an electric current consumption of the switching regulator approaches zero, and converting the intermediate voltage or the input voltage of the power supply circuit to an output voltage using a linear voltage regulator.

Abstract: A decoder and method of decoding a sub-band coded digital audio signal. The decoder comprises: an input, for receiving sub-band coefficients for a plurality of sub-bands of the audio signal; an error detection unit, adapted to analyze the content of a sequence of coefficients in one of the sub-bands, to derive for each coefficient an indication of whether the coefficient has been corrupted by an error of a predefined type; an error masking unit, adapted to generate from the sequence a modified sequence of coefficients for the sub-band, wherein errors of the predefined type are attenuated; a coefficient combination unit, adapted to combine the received coefficients and the modified coefficients, in dependence upon the indication of error; and a signal reconstruction unit, adapted to reconstruct the audio signal using the combined coefficients.

Abstract: A program is executed with a first programmable device (10). Device operating points such as power supply voltage and/or clock frequency are adapted dependent on the states reached by the device during execution. Operation of programs that may have been sold after the device has been supplied to users is optimized by executing the computer program on each of a plurality of programmable devices (10) like the first programmable device, and collecting statistical data associated with the execution states encountered during execution by the plurality of programmable devices (10). Each of the plurality of programmable devices (10) collects its own statistical data and uploads the collected information to a common profiling apparatus (14). The profiling apparatus assigns device operating points to respective ones of the execution states, using an optimization that depends on the combined statistical data from the plurality of programmable devices (10).

Abstract: The present invention, generally speaking, provides for sharing of bandwidth of a shared medium between multiple devices. In one embodiment, the shared medium is structured in accordance with a frame or superframe structure, each frame or superframe having medium access slots of specified time duration defined therein, groups of N contiguous medium access slots defining different allocations zones, groups of M medium access slots defining coordinated sets of medium access slots, wherein the medium access slots of a coordinated set belonging to different allocation zones are equally spaced in time. A device identifies a reservation as regular or irregular, wherein a regular reservation causes the entire medium access slots in one or more coordinated sets to be allocated. In the case of either a regular or an irregular reservation, allocating medium access slots such that a number of unallocated contiguous medium access slots within each allocation zone is maximized.

Abstract: A lamp is provided that is controlled by messages transmitted via a network. The lamp has an internal memory that stores an address and an internal control circuit that responds to received messages that refer to this address. The address is updated when the lamp is installation in a power supply socket, using for example an address from the first message that is transmitted after installation. The lamp contains a detector that detects disconnection of the lamp from the power supply socket, for example by monitoring a resistance value between two parts of one of the power supply terminals of the lamp. In response to this detection the control circuit of the lamp sets information that enables an update of the address in the memory. When it is detected that the lamp is again connected to a power supply socket the address is updated on condition that the update is enabled.

Abstract: A method of dividing a two dimensional array of encapsulated integrated circuits into individual integrated circuit packages uses a first series of parallel cuts (32) extending fully through the leadframe (16) and encapsulation layer (14), and defining rows of the array. The cuts terminate before the beginning and end of the rows such that the integrity of the array is maintained by edge portions (34) at the ends of the rows. After plating contact pads (18), a second series of parallel cuts (36) is made extending fully through the leadframe (16) and encapsulation layer (14). This separates the array into columns thereby providing singulation of packages between the edge portions (34).

Abstract: The invention relates to a memory controller for use in a System-on-Chip, wherein the System-on-Chip comprises a plurality of agents and an off-chip volatile memory. The memory controller comprises a first port (CBP) for receiving low-priority requests (CBR) for access to the volatile memory from a first-subset of the plurality of agents and a second port (LLP) for receiving high-priority requests (LLR) for access to the volatile memory from a second-subset of the plurality of agents, wherein the memory controller is configured for arbitrating between the high-priority requests (LLR) and the low-priority requests (CBR), wherein the memory controller is configured for receiving refresh requests (RFR) for the volatile memory via the first port (CBP), wherein the refresh requests (RFR) are time-multiplexed with the low-priority requests (CBR), wherein the memory controller is configured for treating the low-priority requests (CBR) and the refresh requests (RFR) the same.

Abstract: A program (MC), which can be executed by a programmable circuit, is protected in the following manner. An instruction block (IB) is provided on the basis of at least a portion (MC-P) of the program. A protective code (DS) is generated that has a predefined relationship with the instruction block (IB). The instruction block (IB) is analyzed (ANL) so as to identify free ranges (FI) within the instruction block that are neutral with respect to an execution of the instruction block. The free ranges comprise at least one of the following types: bit ranges and value ranges. The free ranges that have been identified are used for embedding (SEB) the protective code (DS) within the instruction block (IB).

Abstract: In order to provide an interface circuit (100; 100?) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100?), in particular the input of the interface circuit (100; 100?), can be provided with, and/or to the data signals (D; R, G, B).

Abstract: The present invention relates to a detection circuit (100) capable to detect a rectified phase-cut or sinusoidal wave-form using its duty cycle or average value and in response, to select the respective dim mode amongst the linear phase-cut and step-dimming. The circuit (100) receives the rectified waveform with its duty cycle, which is derived through a comparator (22, 24) and converted into a DC signal. The latter which is controlled by the duty cycle is then compared to a reference level (40) through another comparator (20) that, in response, supplies a signal controlling a switching device (30). The switching device (30) will be thus automatically connected either to one set signal level when the DC signal is greater than the reference level (40), namely when the circuit (100) detects a rectified sinusoidal waveform, or to the same level as the DC signal when the DC signal is less than the reference level (40), namely when the circuit (100) detects a rectified phase-cut waveform.

Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.

Abstract: A channel modeling method for Inter Carrier Interference (ICI) cancellation in multi-carrier wireless communication systems comprises: describing the channel with a plurality of fixed matrices and an equal-numbered plurality of unfixed variables; one-to-one pairing each of the described plurality of unfixed variables with one of described plurality of fixed matrices. Corresponding system is also provided. The method and system can compensate for the channel distortion of the Doppler Effect even if the Doppler Frequency Offset is relatively significant.

Abstract: A resistor-equipped transistor includes a package that provides an external collector connection node (114, 134), an external emitter connection node (120, 140) and an external base connection node (106, 126). The package contains a substrate upon which a transistor (102, 122), first and second resistors, and first and second diodes are formed. The transistor has an internal collector (118, 138), an internal emitter (120, 140) and an internal base (116, 136) with the first resistor (104, 124) being electrically connected between the internal base and the external base connection node and the second resistor (108, 128) being electrically connected between the internal base and the internal emitter.

Abstract: A circuit (1202) for a resonant converter (1204; 1326), the resonant converter configured to operate in a burst mode of operation, the circuit configured to: receive a signal (1206; 1308) representative of the output of the resonant converter; compare the received signal (1206; 1308) representative of the output of the resonant converter with a reference signal (1208; 1304) in order to provide an error signal (1310); and process the error signal (1310) in order to provide a control signal (1210; 1328), wherein the control signal (1210; 1328) is configured to set the switching frequency of the resonant converter in order to control the output power during the on-time of a burst of the resonant converter.

Abstract: A method is disclosed of operating a controller for a switch mode power converter and having connection pins, the method comprising a mode-setting phase and an operational phase and comprising: in the mode-setting phase: polling connection pins to sense the presence and/or magnitude of a respective relatively high impedance connected between a respective connection pin and a predetermined electrical potential, and/or other connection pins to sense the presence and/or magnitude of a respective further impedance connected between the respective connection pin and a predetermined electrical potential, and selecting an operational mode from a plurality of possible operational modes; and in the operational phase: operating in the selected operational mode, comprising providing a respective drive signal having a relatively low output impedance from each of the first group of connection pins; and measuring a sense voltage on each of the second group of connection pins.

Abstract: An antenna, in particular a dipole antenna, for radio communication in a hearing aid, is disclosed. The antenna includes a solid three-dimensional dielectric support body, an electrically conductive first plate on a first surface of the support body and an electrically conductive second plate on a second surface of the support body. The first surface and the second surface are arranged on opposing ends of the support body. An electrically conductive filament is arranged on and/or in the support body, electrically coupling the first plate with the second plate, and comprising first sections and second sections. The second sections extend perpendicular to the first sections.

Abstract: There is described a method of controlling application access to predetermined functions of a mobile device (240), the method comprising (a) providing a set of keys, each key corresponding to one of the predetermined functions, (b) receiving (225) an application from an application provider (220, 221, 222, 223) together with information identifying a set of needed functions, (c) generating a signed application by signing the received application with each of the keys that correspond to one of the needed functions identified by the received information, and (d) transmitting (227) information identifying the needed functions and the signed application and a set of access rules to a Secure Element of the mobile device (240). There is also described a device for controlling application access and a system for controlling and authenticating application access. Furthermore, there is described a computer program and a computer program product.

Abstract: A switch mode power converter configured for operation with a plurality of outputs is disclosed. The switch mode power converter includes an inductive element and a resistance in series with the inductive element. The resistance is series with the inductive element is used for determining a current through the inductive element. The resistance is a resistance between the main terminals of a switch in an on-state. The switch have two main terminals and a control terminal and being arranged for directing current through the inductive element to a one of the plurality of outputs.

Abstract: According to an aspect of the invention, an NFC-enabled mobile device for supporting a plurality of proximity services is conceived, wherein each supported proximity service corresponds to a specific operating system running on a specific secure element comprised in the NFC-enabled mobile device, wherein the NFC-enabled mobile device comprises a plurality of data sets and each data set corresponds to a supported proximity service, wherein the NFC-enabled mobile device is arranged to determine whether it supports an advertised proximity service, upon receipt of a service advertisement message comprising a unique identifier of the advertised proximity service from an NFC reader, by searching for the advertised proximity service in said data sets.

Abstract: A tuneable buffer circuit for use in a clock tree has multiple buffers in parallel, each buffer having a grounding function, and also a bypass switch in parallel with the buffers. The circuit has a normal mode of one buffer connected into circuit, a first low voltage mode of multiple buffers connected into circuit in parallel without grounding function, a second low voltage mode of the buffers connected into circuit in parallel with grounding function and a bypass mode.