Abstract: Disclosed is a method and apparatus for managing transmit requests among a plurality of co-located transmitting devices each associated with a wireless transmitting protocol. The method comprises the steps of determining the cost associated with each of the transmit requests, wherein the cost is associated with the cost of granting the request and the cost of rejecting the request, granting the request associated with the lowest cost, and rejecting all other requests. In another aspect of the invention, the method comprises the step of determining whether the lowest cost is acceptable and rejecting the request associated with the lowest cost when the lowest cost is unacceptable.

Abstract: The present invention provides a method and apparatus for compensating the output of a transmitter stage (50) of a communications system. A communications apparatus has a transmitter stage (50) providing a variable control voltage which varies the power of the transmitter stage. The impedance at the output of the transmitter stage. (50) varies as the power varies. A control generation circuit compares a reference voltage to the variable control voltage to produce a control signal (VvswrC). A compensated load (40) coupled to the output of the transmitter stage (50) has active component (s) whose' impedance varies in response to the control signal (VvsweC) so as to compensate for the impedance at the output of the transmitter stage (50).

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: A battery comprises a carrier foil, with solid state battery elements spaced along the foil and mounted on opposite sides of the foil in pairs, with the battery elements of a pair mounted at the same position along the foil. The carrier foil is folded to define a meander pattern with battery element pairs that are adjacent each other along the foil arranged back to back.

Abstract: A power factor controller is disclosed, in which error feedback is provided my means of a parallel combination of at least two error feedback channels. By providing at least two error feedback channels, the stability associated with, for instance, a continuously integrated feedback loop with relatively long time constant, may be combined with a fast transient response associated with, for instance, a sample-and-hold error feedback. A method of operating such a power factor controller is also disclosed.

Abstract: A method of manufacturing an integrated circuit having a substrate comprising a plurality of components and a metallization stack over the components, the metallization stack comprising a first sensing element and a second sensing element adjacent to the first sensing element.

Abstract: Disclosed is a method of manufacturing a discrete semiconductor device package (100), comprising providing a wafer comprising a plurality of semiconductor devices (50), each of said semiconductor devices comprising a substrate (110) having a top contact (130) and a bottom contact (150); partially sawing said wafer with a first sawing blade such that the semiconductor devices are partially separated from each other by respective incisions (20); lining said incisions with an electrically insulating film (160); and sawing through said incisions with a second sawing blade such that the semiconductor devices are fully separated from each other. A resulting discrete semiconductor device package (100) and a carrier (200) comprising such a discrete semiconductor device package (100) are also disclosed.

Abstract: A method and apparatus are disclosed wherein positioning data and road charging data depending on a vehicle position may be inserted into a combined data stream. The positioning data and road charging data may be provided with the same protocol type such as a national marine electronics association, NMEA, protocol or NMEA 0183 protocol. The combined data stream therefore comprises a mixed sequence of positioning data protocol messages and road charging data protocol messages.

Abstract: An electric device has a resistor including a phase change material changeable between a first phase and a second phase within a switching zone. The resistor has a first resistance when the phase change material is in the first phase and a different second resistance, when the phase change material is in the second phase. The resistor may conduct a first current. The device has a heating element that may conduct a second current for enabling a transition of the phase change material from the first to the second phase. At the position of the switching zone, the resistor is arranged as a first line and the heating element is arranged as a second line. The first and second line may conduct the first current and the second current respectively, wherein the first line and the second line cross at the position of the switching zone.

Abstract: Various embodiments relate to a transmission circuit and related method of shaping the transmission spectrum of a carrier signal. The transmission circuit may comprise a plurality of switching amplifier stages that are controlled by a modulation sequence produced by a transmission (TX) modulator. The TX modulator may receive the transmission data as a sequence of bit groups and may produce a modulation sequence including a plurality of control bits that may drive each of the switching amplifier stages. In some embodiments, one or more pulse-shaping filters may modify in-phase (I) and quadrature (Q) phase components of the transmission data. The modified components may directly shape spectral content of the output signal produced by a transmission driving circuit. Higher quantities of amplifier stages included in the transmission driving circuit may add higher granularity to the shape of the spectrum of the output signal.

Abstract: Example embodiments are directed toward configuration of a phase lock loop (PLL) circuits for low power operation. In particular embodiments, a fraction related to a desired gain of a PLL circuit is determined. A set of possible frequency-divider values and a set of possible feedback divider values are determined. A PLL configuration is selected from a combination of the sets of frequency divider and feedback divider values that forms a ratio indicated the determined fraction.

Abstract: Various embodiments relate to a reconfigurable integrated digital Chireix out-phasing power amplifier for use in high power base stations is described and a related method of said design. The power amplifier may include a power transistor circuitry having plurality of power transistors and shunt-series circuitry (L1C1, L2C2), a broadband combiner having Chireix compensation elements, and an impedance matching filter. In one embodiment, the power amplifier is implemented in a real switch-mode to facilitate integration of the Chireix compensation elements so as to make the Chireix power amplifier tunable. A method of driving Chireix power amplifier structure is also described. In some embodiments, a variable supply voltage may power the transistor circuitry based on the desired output power of the Chireix power amplifier. In some embodiments, the variable supply voltage may depend upon an out-phasing angle between the two drivers in the transistor circuitry.

Abstract: A lighting unit comprises a packaging substrate (10) formed from a semiconductor, a channel (12) formed in the substrate and a discrete light emitting diode arrangement (34) in the channel. A surface region of the channel comprises doped semiconductor layers (20, 24) which define a light sensor. The arrangement provides a light sensor (which can be used to determine colour and/or output flux) for a LED unit, with the light sensor embedded in substrate used for packaging. This provides a low cost integration process and provides good registration between the light sensor and the LED output.

Abstract: The present invention relates to a method and a device (11) using a physical token (14), which provides measurable parameters, to derive at least one data set. A plurality of values of one or more of the parameters are measured. From these measured values, a measure of variance is calculated. Quantization intervals into which a measured value is to be quantized are then determined. A possible value of a data set, which subsequently can be derived from a measured value provided by the physical token, is associated with each quantization interval. Further, information which subsequently enables determination of these quantization intervals is stored. Hence, an enrolling phase has been completed. When the preparing phase has been completed, a deriving phase may commence. When a data set is to be derived, for example to be used as a cryptographic key, a value of any one of the parameters provided by the PUF is measured.

Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed paral

Abstract: The present invention relates to a circuit and a method for automatic common-mode rejection calibration in a differential conversion system and unbalance compensation for balancing the operation point of a circuit in the signal path and for enhancing the common-mode rejection.

Abstract: A wafer comprises i) at least one independent die having internal integrated components, a multiplicity of internal pads connected to some of the internal integrated components, ii) scribe lanes defined between and around each independent die, and in part of which are defined, for each die, at least a first group of external pads and/or a second group of external test integrated components. The external pads of each first group are connected, through conductive tracks, to a chosen one of the internal pads and/or internal integrated components of the associated die, and arranged to be fed with chosen test signals or to collect test result signals. Each external test integrated components of each second group is connected, through conductive tracks, to a chosen one of the die internal pads and/or die internal integrated components and/or to external pads of a first group.

Abstract: A microcontroller (30) includes a processor (32), an embedded memory (46) operatively coupled to the processor (32), and a microcontroller test interface (34) operatively connected to the processor (32) and the memory (36). The microcontroller (30) responds to a reset signal to perform a reset initiation that causes an initial disabled state of the test interface (34) to be set and execution of initiation code with the processor (32). This code execution optionally establishes a further disabled state. The microcontroller (30) provides an enabled state of the test interface for memory (46) access through the test interlace (34) during microcontroller (30) operation subsequent to the reset initiation unless the further disabled memory (46) access state is established by execution of the initiation code.

Abstract: The invention relates to an integrated circuit card (1) comprising: an input/output block (4) for receiving external command data from an interface device (2); a central processing unit (CPU) (3) in signal communication with the input/output block (4) for performing a task corresponding to the received command data; a judgement block (5) in signal communication with the central processing unit (3) for judging whether a working time of the central processing unit (3) reaches a reference time, after an input of the external command data is completed; and a control block (6) in signal communication with the judgement block (5) for operating responsive to an output of the judgement block, wherein the control block controls such that a S(WTX request) is output via the input/output block (4) without intervention by the central processing unit whenever the interface device (2) connected to the integrated circuit card (1) transmits a command to the integrated circuit card and the integrated circuit card is not able t

Abstract: A data processing arrangement (MPS) comprises a plurality of data processors (SPR, PM1, . . . , PM4) that can be reset individually. A reset module (RSM) handles various reset request signals (HRG, SRG, SRP1, . . . , SRP4) in accordance with a prioritization and timing scheme so as to obtain respective reset signals (GRS, PRS1, . . . , PRS4) for respective data processors (SPR, PM1, . . . , PM4). The reset module (RSM) preferably comprises a reset request register, which stores respective reset requests that the respective reset request signals convey, and a request execute register, which stores respective granted reset requests that the reset signals convey.