Abstract: A switching amplifier (200; 300; 400; 500) comprising: a switch (202; 302) configured to electrically connect and disconnect a first pin (202a; 302a) of the switch (202; 302) to a second pin (202b; 302b) of the switch (202; 302) in accordance with a pulse width modulated input signal (216; 316; 516). The second pin (202b; 302b) is connected to a ground connector (204; 304). The switching amplifier also comprises a feed inductor (206; 306; 406) connected between a voltage supply connector (208; 308) and the first pin (202a; 302a) of the switch (202; 302), and a circuit (210; 310; 522) comprising a variable component having a variable imaginary impedance. The circuit (210; 310; 522) is connected between the first pin (202a; 302a) of the switch (202; 302) and an output connector of the amplifier (212; 312.

Abstract: A resonator device (200) comprises a base (206) comprising an anchor (204) and a vibration unit (212) connected to the anchor (204). The vibration unit (212) is configured to have a first vibration mode (218) and a second vibration mode (216) different from the first vibration mode (218). According to an embodiment, the vibration unit (212) is configured such that the first vibration mode (218) and the second vibration mode (216) destructively interfere at the anchor (204).

Abstract: A battery cell measurement system comprising a signal generator coupled to a pulse density modulation circuit generating a control signal which drives a switch connected between a first terminal of a battery cell and a first terminal of a bleeding impedance, a second terminal of the bleeding impedance being coupled to a second battery cell terminal. The first terminal is coupled to a first terminal of a second switch. The second terminal is coupled to a first terminal of a third switch. A second terminal of the second switch and second terminal of the third switch are coupled and are further coupled to a low-pass filter. A signal generated by the low-pass filter is inputted into an analog to digital converter, which provides a signal representative of either a signal across the bleeding impedance, or a signal between the battery cell terminals.

Abstract: An electronic device comprising a passive harmonic-rejection mixer (400) and a calibration circuitry (425). The passive harmonic rejection mixer has an input (102) connected to several sub-mixer stages (402), and the sub-mixer stages are connected to a summing module (406, 408) for generating the output (104). Each sub-mixing stage comprises a gating module (414), an amplifier (416), and a weighting module (418), the gating module selectively passing the input signal or the input signal with inverted polarity under the control of control signals. The calibration circuitry (425) is adapted to input a reference signal (430) to the input of the mixer, receive an output signal (104) from the output of the mixer, and set the weights (K1, K2, K3, K4) of the weighting modules to make the output signal match an expected output signal.

Abstract: A display device comprises a substrate which carries an array of pixels. Each pixel comprises an array of apertures in the substrate, each aperture of the array having a maximum opening dimension less than the wavelength of the light to be transmitted through the aperture. The effective dielectric constant of the aperture and/or the dielectric constant of the substrate is varied, thereby to vary the light transmission characteristics of the pixel between transmission of at least one frequency in the visible spectrum and transmission of substantially no frequency in the visible spectrum.

Abstract: An electrical circuit for emulating a capacitance, comprises a physical capacitor which is charged by charge flow from the input of the electrical circuit. An amplifier amplifies the voltage at the input of the electrical circuit such that the physical capacitor is charged with a larger change in voltage than the change in voltage at the input. This implements an effective multiplication of capacitance. A reset system resets the physical capacitor without drawing charge from the input of the electrical circuit. This extends the voltages which can be provided to the input.

Abstract: A matching network is integrated into a multilayer printed circuit board containing an RFID integrated circuit to provide both an antenna and a matching network for the RFID integrated circuit in the ultra high frequency regime.

Abstract: An audio amplifier (3) for a mobile telephone (1) is disclosed. The audio amplifier (3) comprises first and second output stages (11, 12), each for coupling to a respective one of first and second loudspeakers (4, 5), and switching circuitry (10) adapted to respond to a switching signal by switching an output signal from a common input stage (7, 8, 9) to the first output stage (11) when the switching signal is in a first state and to the second output stage (12) when the switching signal is in a second state.

Abstract: A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication.

Abstract: Integrated circuit (20) comprising several different voltage rails (V5 to V1) and an on-chip ESD protection circuit. The ESD protection circuit comprises at least one group (21, 22, 23) of ESD clamp devices (C1-C4). The ESD clamp devices (C1-C4) are arranged in a ladder-configuration. This ladder-configuration is characterized in that there is one of the ESD clamp devices interposed between each of the power rails (V5 to V1) and the respective power rail having a next lower voltage. Due to this arrangement an ESD current path is defined between each one of the power rails and the power rail having the next lower voltage. The ESD clamp devices (C1-C4) are off under normal power operation of the integrated circuit (20).

Abstract: A memory device including a non-volatile re-programmable memory cell is provided. In connection with various example embodiments, the memory cell is a single resistor located between a first and second node. The resistor stores different resistance states corresponding to different resistance values set by SiCr-facilitated migration. The SiCr-facilitated migration occurs in response to energy presented between the first and second nodes. The application of a signal to a first node of the memory cell resistor forces the migration of elements along the memory cell resistor to set the resistance value of the memory cell resistor. The application of a second signal of approximately equal strength to the second node reverses the change and resistance and returns the memory cell to the previous resistance level. In some implementations the resistor is made of SiCr.

Abstract: High Speed I/O interfaces such as DVI, S-ATA or PCI-Express require expensive test equipment. Loop-back tests are widely used as one alternative, but lack coverage of timing-related defects. A system and method for on-chip jitter injection using a variable delay with controllable amplitude and high accuracy is provided that improves the coverage of loop-back tests.

Abstract: The invention relates to a method and a system for transmitting data from a medium access control device (2) via a digital interface (IF1) to a physical layer (4) and to an antenna (5), wherein the physical layer (4) comprises a base band (4) with a base band controller (7) and a data processing pipeline (3) comprising a plurality of functional blocks (FB1 . . . 13), comprising the steps of: detecting an end of a frame of payload data, which leaves the antenna (5), at a predetermined point (P1 to P3) within the data processing pipeline (3), especially at the end of the data processing pipeline (3), thereupon, starting a timer (T1) for delaying a de-assertion of an activity signal (PHY_ACTIVE) of the physical layer (4), and after expiration of the timer (T1), de-asserting the activity signal (PHY_ACTIVE).

Abstract: It is described a bond pad structure and a method for producing the same, the bond pad structure (1), comprising: a substrate (3) having a surface (17) to be electrically contacted; a first isolator layer (5) contacting the surface (17) of the substrate in a first region (a); a first metal layer (9) contacting the surface (17) of the substrate (3) in a second region (b) adjacent the first region (a) and partly overlapping the first isolator layer (5); a second isolator layer (11) at least partly overlapping the first isolator layer (5) and the first metal layer (9); a second metal layer (13) at least partly overlapping the second isolator layer (11) in the second region (b); wherein a maximum thickness (U) of the second metal layer (13) perpendicular to the surface (17) of the substrate (3) is smaller than a maximum thickness (t0) of the first isolator layer (5) perpendicular to the surface (17) of the substrate (3).

Abstract: The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (16), a control gate (19) and a separate erase gate (10). The erase gate (10) is provided in or on isolation zones (2) provided in the substrate (1). Because of that, the erase gates (10) do not add to the cell size. The capacitance between the erase gate (10) and the floating gate (16) is small compared with the capacitance between the control gate (19) and the floating gate (16), and the charged floating gate (16) is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate (10) and the floating gate (16).

Abstract: A low-drop out (LDO) regulator circuit is provided having a gate of a pass transistor coupled to an output of an operational transconductance amplifier, the LDO regulator exhibiting a non-dominant pole at an output of the LDO. A dynamic zero-compensation circuit is coupled in parallel to the pass transistor. A compensation control circuit is coupled and configured to adjust a frequency, at which a zero is generated, and cause the generated zero to track with the non-dominant pole.

Abstract: A lamp is provided that is controlled by messages transmitted via a network. The lamp has an internal memory that stores an address and an internal control circuit that responds to received messages that refer to this address. The address is updated when the lamp is installation in a power supply socket, using for example an address from the first message that is transmitted after installation. The lamp contains a detector that detects disconnection of the lamp from the power supply socket, for example by monitoring a resistance value between two parts of one of the power supply terminals of the lamp. In response to this detection the control circuit of the lamp sets information that enables an update of the address in the memory. When it is detected that the lamp is again connected to a power supply socket the address is updated on condition that the update is enabled.

Abstract: A user-interface for controlling a data processing system using a joystick includes a joystick for controlling input to the data processing system. The joystick has a pivoting component for assuming tilted positions by tilting in directions that lie in a reference plane associated with the component, and a sensor for sensing at succeeding sampling moments the direction corresponding to succeeding tilted positions of the component, and a difference determination device for determining a difference in direction between a first direction sensed at a first sampling moment and a second direction sensed at a second sampling moment after the first moment, and a parameter modifier for modifying a value of a parameter of the data processing system by adding or subtracting a difference value that depends upon the difference in direction.

Abstract: Disclosed is a shift register (200, 400) comprising an input (205), an output (230) and a plurality of register cells (210) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer (220) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels (230, 410) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

Abstract: The present invention relates to the field of photovoltaic systems with solar cell (s) or modules having insolation differences or mismatch. Each solar module is formed by placing a large number of solar cells in series. The PV system is then formed by placing a number of solar modules in series in a string and sometimes by placing multiple strings of series-connected solar modules in parallel, depending on the desired output voltage and power range of the PV system. In practical cases, differences will exist between output powers of the solar cells in the various modules, e.g. due to (part of) the modules being temporarily shaded, pollution on one or more solar cells, or even spread in solar-cell behaviour that may become worse during aging. Due to the current-source-type behaviour of solar cells and their series connection these differences will lead to a relatively large drop in output power coming from the PV system.