Abstract: It is described a current interface (100, 200) with a blocking capacitor (128, 228). The blocking capacitor (128, 228) is attached to an additional pin (115, 215), thus allowing a supply voltage ripple rejection of an internal sensor circuit (130, 230). The supply lines (160, 260, 170, 270) are decoupled from the capacitor (128, 228) by a diode (125) or by a voltage regulator (226). Thereby, the use of a sensor element (132, 232) with the current interface (100, 200) does not restrict the size of the blocking capacitor (128, 228) because transient times of edges of output current signals of the current interface (100, 200) are not affected by a low-pass behavior of the blocking capacitor (128, 228) combined with a sensing resistor (171, 271) being typically used for measuring the amperage of the output current signals.

Abstract: The invention relates to a tamper-resistant semiconductor device comprising a substrate (5) comprising an electronic circuit arranged on a first side thereof. An electrically-conductive protection layer (50, 50a, 50b) is arranged on a second side of the substrate (5) opposite to the first side. At least three through-substrate electrically-conductive connections (45) extend from the first side of the substrate (5) into the substrate (5) and in electrical contact with the electrically-conductive protection layer (50, 50a, 50b) on the second side of the substrate (5). A security circuit is arranged on the first side connected to the through-substrate electrically-conductive connections (45) and is arranged for measuring at least two resistance values (R12, R23, R34, R14, R13, R24) of the electrically-conductive protection layer (50, 50a, 50b) through the through-substrate electrically-conductive connections (45).

Abstract: A method of operating a RF device having a first RF gain stage (34) comprising a programmable attenuator (36) coupled to a RF amplifier (38) and a second narrowband gain controlled amplifying stage (24) for amplifying a signal in a wanted bandwidth, comprises selecting a gain setting of the first RF gain stage to maximize the signal-to-noise (SNR) by minimizing the total noise in a wanted signal and a gain setting of the second narrowband amplifying stage to provide a substantially constant level output. In order to select the gain setting of the first RF gain stage, the RF device includes a control stage (40) which takes into account the gain settings of the first RF stage and the second gain controlled amplifying stage, the distortion noise (referred to the RF input) and the thermal noise (referred to the RF input) when selecting a gain setting to be applied to the programmable attenuator to minimize the total noise.

Abstract: The invention relates to a method and a system for calibrating an analogue I/Q-modulator (2) of a transmitter (3), wherein a calibration signal (s(tk)) is transmitted and an in-phase signal (sI(tk)) and a quadrature-phase signal (sQ(tk)) of the calibration signal (s(tk)) are adjusted by at least one predetermined compensation coefficient (C, D, E) in two calibration steps in at least one compensation measurement set (un, Vn, Wn), whereby: —in a first calibration step, the calibration signal (s(tk)) is adjusted by a first complex compensation value (Cn,1, Dn,1, En,1) and an output signal of the detector circuit (20) is correlated with a harmonic (H1, H2) of said calibration signal (s(tk)) to yield a first complex compensation measurement result (un,1, Vn, 1, Wn,1), —in a second calibration step, the calibration signal (s(tk)) is adjusted by a second complex compensation value (Cn,2, Dn, 2, En,2) and the output signal of the detector circuit (20) is correlated with said harmonic (H1, H2) of said calibration sig

Abstract: In order to provide a device (100) as well as a method for event-triggered communication between and among a plurality of nodes (A, B, C, S), in particular between and among a plurality of mobile nodes, for example between and among a plurality of vehicles, where the aspect of acknowledging the messages is taken into consideration, it is proposed to address at least one message (M1, M2, M3), in particular at least one identifying message (IM) and/or at least one acknowledging notification (AM), to at least one specific node (A, B, C, S), in particular by way of unicast transmission.

Abstract: A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

Abstract: A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.

Abstract: A sample-and-hold amplifier (400) having a sample phase of operation and a hold phase of operation. The sample-and-hold amplifier comprising one or more sampling components (404, 406) configured to sample input signals during the sample phase of operation, and provide sampled input signals during the hold phase of operation, and an amplifier (402) configured to pre-charge the output (416, 418) of the sample-and-hold amplifier (400) during the sample phase of operation, and buffer the sampled input signal during the hold phase of operation.

Abstract: A method of manufacturing a semiconductor device is presented. The device has: a gate terminal formed from polysilicon and covered by an insulation layer; and a plug extending through an insulation layer to provide an electrical connection to the gate trench. A metal layer is deposited to cover at least a portion of the insulation layer. The metal layer is then etched to remove the metal layer from above the plug.

Abstract: A phase change memory cell has more than one memory region (14,18) each being a narrowed region of phase change memory material (2) extending between first and second electrodes (4,6). Each of the plurality of memory regions (14, 18) can be programmed to be in a low resistance state or a high resistance state by applying suitable programming conditions of current and/or voltage. The resistances of the high resistance states and the programming conditions to convert the high resistance states to the low resistance state are different in each of the plurality of memory regions.

Abstract: The present invention relates to a method of assembling a first data stream (ds1) with a second data stream (ds2), each data stream comprising coded frames (I,P), each coded frame being associated with a relative time value, specific coded frames of a data stream being preceded by an absolute time value. Said method comprises the steps of: calculating a current reference time value for a current coded frame on the basis of a previous reference time value and on an integer part of the current relative time value, calculating an offset time value on the basis of the reference time value of the last frame in the display order of the first data stream, modifying the absolute time values of the specific coded frames of the second data stream by adding the offset time value to said absolute time values.

Abstract: An integrated circuit is provided that comprises a substrate of silicon and an interconnect in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallization layer on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.

Abstract: A microelectronic package (31) has a microelectronic device, which is encapsulated in a quantity of material (27), and a lead frame element (15) for enabling the microelectronic device to be electrically contacted from outside of the package (31). The lead frame element (15) comprises at least two elongated members (11) comprising electrically conductive material and a filling material (12) comprising electrically insulating material, wherein the members (11) are partially embedded in the filling material (12). The lead frame element (15) is manufactured by providing elongated members (11), positioning the members (11) according to a predetermined configuration, providing filling material (12) to spaces (13) which are present between the members (11), and possibly removing portions of the filling material (12) and the members (11) in order to expose the electrically conductive material of the members (11).

Abstract: An integrated circuit having an on-chip access right manager to grant or deny access to a memory segment to a peripheral device such as a CPU (Central Processing Unit), DSP (Digital Signal Processor) or DMA (Direct Memory Access) unit according to predetermined access rights upon reception of a read instruction from the peripheral device, and an on-chip lock connected to a memory data bus, the lock being controllable by the access right manager to block access to a logical one or zero set on each memory data bus wires as long as the access to the memory segment is not granted. Upon reception of the read instruction from the peripheral device, the integrated circuit is configured to start both the process of setting, by the on chip memory, of either a logical one or a logical zero on each of the wires of the memo data bus, as well as the process of granting or refusing the access to the memory segment by the on-chip access right manager to the peripheral device.

Abstract: An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by incorporating the series of inverters in a ring oscillator.

Abstract: A system comprises a chip (71) and a substrate (78). The chip (71) comprises a circuitry and a mounting surface (83) with first and second contacts (73, 74, 75, 76). The substrate (78) comprises a surface (90) with first and second contact pads (79, 80) and an electrically conductive pad (91) connected to the first contact pad (79) by a low-resistive connection (93). The chip (71) is attached to the substrate (78) so that the mounting surface (83) is spaced apart from the first contact pad (75) and the electrically conductive pad (91). The mounting surface (83) overlaps partly the first contact pad (79) with a first overlapping area (B1) resulting in a first stray capacitor (C1) and the electrically conductive pad (91) with a second overlapping area (B3) resulting in a second stray capacitor (C3).

Abstract: A device has an electroacoustic interface between interfaces for balanced electrical signals and unbalanced electrical signals (i.e. a balun) includes a film of piezoelectric material having a first and second pair of electrodes on a first surface a common electrode, with at least partial overlaps with all of the electrodes of the first and second pair, on a second surface. The interfaces between the electrodes in the first and second pair have geometrically identical shapes. Piezoelectrically polarized regions are provided in the film at the overlaps of the electrodes with the electrode arrangement. The direction of polarization components of the regions in the overlaps with the first electrode and the second electrode in the first pair are equal to each other. To provide for balun coupling, the directions of the polarization components in the overlaps with the first electrode and the second electrode in the second pair are mutually opposite.

Abstract: A circuit (12) comprises a first circuit point (13) and a second circuit point (14), which first circuit point (13) and second circuit point (14) are designed to be connected with RF transmission means (11) being designed for receiving in a contact-less manner a carrier signal (CS) from a read/write station and for feeding the circuit (12) with the received carrier signal (CS). The circuit (12) further comprises circuit testing means (4) being designed to carry out functional tests of the circuit (12) and to output a modulated response signal (TS-MOD) via the first and second circuit points (13, 14) only if the functional tests have been successful.

Abstract: An integrated circuit has an inhomogeneous protective layer or coating over a circuit to be protected, and a sensing circuit (80) arranged to sense a first impedance of a part of the protective coating compared to a reference impedance (CO) located on the integrated circuit. The sensing circuit is able to measure a change in the first impedance, e.g. caused by tampering. The sensing circuit has an amplifier (OTA) having a feedback loop, such that the impedance being sensed is in the feedback loop. The sensing circuit can be incorporated in an oscillator circuit (OTA, Comp) so that the frequency depends on the impedance. Where the impedance is a capacitance, sensing electrodes adjacent to the protective layer or coating, form the capacitance. The electrodes can be arranged as selectable interdigitated comb structures, so that the protective layer or coating extends in between the teeth of the comb structures.

Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.