Abstract: An example apparatus includes a discernment logic circuit and logic circuitry. The discernment logic circuit discerns whether a requested communications transaction received over the management communications bus from another of the plurality of logic nodes involves a first type of transaction or a second type of transaction. The second type of transaction has a plurality of commands associated with the requested communication transaction to convey respectively different parts of the requested communications transaction including an address part and a data part. The logic circuitry accesses, in response to discerning that the requested communications transaction involves the second type of transaction, a register of the plurality of registers associated with the first type of transaction, wherein the plurality of registers associated with the first type of transaction are mapped into a set of addresses for the second type of transaction.

Abstract: An example an apparatus includes a register set, data access circuitry, and configuration circuitry. The register set includes at least one addressable register to store data and to manifest a side effect in response to the at least one addressable register being accessed. The data access circuitry accesses the register set, which may cause the side effect, and the configuration circuitry selectively disables the side effect.

Abstract: A device is disclosed. The device includes a plurality of ports to receive a plurality of audio streams, an audio content control unit configured to modify playback length of an audio content of at least one of the plurality of audio streams according to an input time interval, an audio decoder and a memory buffer coupled to the audio decoder and the audio content control unit. The memory buffer is used by the audio content control unit to buffer at least one of the plurality of audio streams.

Abstract: Embodiments are provided for a packaged semiconductor device including: a semiconductor die having an active side and an opposite back side, the semiconductor die including a magnetoresistive random access memory (MRAM) cell array formed within an MRAM area on the active side of the semiconductor die; and a top cover including a soft-magnetic material positioned on the back side of the semiconductor die, wherein the top cover includes a recess formed in a first major surface of the top cover, the first major surface faces the back side of the semiconductor die, and the recess is positioned over the MRAM cell array.

Abstract: An apparatus is disclosed that includes a phase detector circuit for generating a first pulse signal based on first and second input clock signals. A first circuit adjusts the first pulse signal by delaying transmission of a leading edge of the first pulse signal, but not a trailing edge of the first pulse signal. A charge pump circuit charges or discharges a capacitor based on the adjusted first pulse signal, and a voltage controlled oscillator (VCO) circuit generates an output clock signal with a frequency that depends on a voltage on the capacitor.

Abstract: A Controller Area Network (CAN) transceiver is disclosed. The CAN transceiver includes a CAN bus interface including CANH and CANL inputs, a TXDC interface, RXDC interface and a CAN bus diagnostics module coupled with the CAN bus interface. The CAN bus diagnostics module is configured to analyze the CAN bus interface to detect and error on the CANH and CANL inputs and send a diagnostics code predefined for the detected error to one of the TXDC interface and the RXDC interface.

Abstract: A power switch over current protection system including a power switch transistor configured to deliver a power current from a power source to power load, a power switch driver configured to control and on/off state of the power switch, an over current protection (OCP) circuit to detect a threshold value of the power current, a discharge transistor configured to discharge a parasitic capacitance of the power switch transistor, and a system state machine to receive a signal from the OCP circuit configured to control an action of the power switch driver and discharge transistor depending on the level of the power current.

Abstract: A sigma-delta analog-to-digital converter (ADC) includes a feed-forward circuit, a finite-impulse-response (FIR) digital-to-analog converter (DAC), and a decimation filter. The feed-forward circuit is configured to receive an analog input signal and a feedback signal and generate a set of digital signals. Each feedback element of the FIR DAC includes a flip-flop and a reset circuit. The reset circuit is configured to receive a corresponding reset signal of a set of reset signals and output a reference output signal when the corresponding reset signal is deactivated. The reset signal of each feedback element is deactivated sequentially after each cycle of a clock signal that is received by the flip-flop associated with a corresponding reset circuit of each feedback element. The feedback signal is generated based on the reference output signal. The decimation filter is configured to generate a digital output signal based on the set of digital signals.

Abstract: A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition is formed at the minor surface of the substrate. The eutectic alloy composition is removed from the minor surface of the substrate such that a portion of the eutectic alloy composition remains at an outer perimeter of the minor surface to strengthen the outer perimeter of the substrate. A bonding layer is deposited over the minor surface and over the portion of the eutectic alloy composition at the outer perimeter of the minor surface. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures. Additional eutectic alloy composition may remain on the minor surface of the substrate at the streets to strengthen the substrate during device wafer separation.

Abstract: In connection with a frequency modulated (FM) communications system, exemplary aspects concern processing a desired channel of a frequency modulated (FM) signal based on an indication of an amplitude-level difference between a measured amplitude of a desired channel in the FM broadcast signal and a measured amplitude of another (possibly-interfering) channel. Based on such amplitude-level difference indication, an approach is selected for estimating the frequency spectrum of the other (possibly-interfering) channel in the FM broadcast signal. The selected approach may differ depending on whether the amplitude-level difference corresponds to an amplitude-level difference for which a frequency spectrum of the desired channel may be determined via a coarse estimate or via a less-coarse estimate of the frequency spectrum of the other channel.

Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

Abstract: A signal processor comprising: an input terminal, configured to receive an input-signal; a voicing-terminal, configured to receive a voicing-signal representative of a voiced speech component of the input-signal; an output terminal; a delay block, configured to receive the input-signal and provide a filter-input-signal as a delayed representation of the input-signal; a filter block, configured to: receive the filter-input-signal; and provide a noise-estimate-signal by filtering the filter-input-signal; a combiner block, configured to: receive a combiner-input-signal representative of the input-signal; receive the noise-estimate-signal; and combine the combiner-input-signal with the noise-estimate-signal to provide an output-signal to the output terminal; and a filter-control-block, configured to: receive the voicing-signal; receive signalling representative of the input-signal; and set filter coefficients of the filter block in accordance with the voicing-signal and the input-signal.

Abstract: A hash accelerator is provided that receives a hash key value from a processor core, determines a main memory address storing a hash table entry corresponding to the hash key value, and causes the hash table entry to be stored in a cache memory accessible by the processor core. The hash accelerator is configured to execute the same hash function that the processor core executes, and if the hash accelerator is faster than the software executing on the processor core, the hash table entry can be available to the core processor from cache memory by the time the processor core attempts to access the entry. This avoids a cache miss by the processor core, thereby improving overall efficiency of routines executed by the processor core.

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a physical layer (PHY) device that is compatible with the IEEE 802.3 standard is disclosed. The PHY device includes a physical coding sublayer transmitter (PCS-TX), a physical medium attachment transmitter (PMA-TX), a physical coding sublayer receiver (PCS-RX), a physical medium attachment receiver (PMA-RX), and a media access priority manager configured to initiate transmission of an indication of a priority of a frame that is to be transmitted onto a shared media, where the indication of the priority of the frame includes more than three bits of frame priority information.

Abstract: This specification discloses devices and methods that provide for an improved switched mode power supply (SMPS) with a supply voltage connected p-type active clamp. In some embodiments, such an improved SMPS can have a p-type active clamp connected on one side to a positive voltage (which can preferably be the supply voltage), and on the other side to a clamp capacitor. Such an improved SMPS would then have the benefit of not requiring additional components (such as a level shifter, a high side supply voltage, a negative supply voltage, etc.) and the costs associated with these additional components.

Abstract: A system-on-chip (SoC) includes first and second processing circuits and a data exchange circuit such that the first processing circuit is configured to process image lines based on corresponding sets of processing attributes. The first processing circuit is further configured to continuously receive and process the image lines one after the other to generate corresponding output data, and the second processing circuit is configured to continuously receive by way of the data exchange circuit, the generated output data for processing the generated output data. The data exchange circuit is thus configured to control data flow between the first processing circuit and the second processing circuit such that the first processing circuit and the second processing circuit parallelly process corresponding data associated with same or different image lines.

Abstract: An error recovery system, method, and apparatus are provided for a microcontroller unit (100) having a plurality of components (101-109) by assigning error recovery actions to at least a first MCU component to specify a component-specific operation for returning the first MCU component to a known state to restart operation of the first MCU component from the known state, and then storing the assigned error recovery actions in a recovery lookup table (122) so that a fault collection and control unit can use a hardware state machine (121) to evaluate an error signal received from an MCU component for determining an error type and location for the MCU component which are applied to the recovery lookup table to retrieve and apply the error recovery actions to return the first MCU component to the known state without restarting all other components on the MCU.

Abstract: In accordance with a first aspect of the present disclosure, an active load modulation (ALM) transceiver is provided, comprising a transmitter configured to send a transmit signal to an external device, wherein the transceiver is configured to adjust one or more parameters of the transmit signal at the end of at least one burst of said transmit signal. In accordance with a second aspect of the present disclosure, a method of operating an active load modulation (ALM) transceiver is conceived, comprising sending, by a transmitter of the transceiver, a transmit signal to an external device, and adjusting, by the transceiver, one or more parameters of the transmit signal at the end of at least one burst of said transmit signal.

Abstract: An embodiment of a transformer-based system or galvanic isolation device includes a first coil, a second coil aligned with the first coil across a gap, and a first capacitor coupled between the first coil and a first voltage reference. A first electrode of the first capacitor may be formed from a conductive electrode structure that is electrically isolated from the first coil, and a second electrode of the first capacitor may be formed from at least a portion of the first coil. The system or device also may include a second capacitor coupled between the second coil and a second voltage reference. The first and second coils may form portions of first and second IC die, respectively, and the system or device may also include one or more dielectric components within the gap between the IC die, where the dielectric component(s) are positioned directly between the first and second coils.

Abstract: An example apparatus (100) is for use for use with front-end circuitry (102) to transmit and receive radar wave signals, The apparatus (100) includes digital phase locked loop (PLL) circuitry (104) and a control circuit (106). The digital PLL circuitry (106) provides a chirp sequence with frequency modulated continuous wave signals (FMCW), the FMCW signals being chirps containing a start frequency and a stop frequency, representing a selected chirp bandwidth (BW). The digital PLL circuitry (104) includes the DCO circuit (108) which frequency resolution is configured and arranged to be tuned relative to the selected chirp BW, the frequency resolution configured in response to a selected level of capacitance. The control circuit (106) controls the selected level of capacitance used by the DCO circuit (108) by changing the frequency resolution of the DCO according to the selected chirp BW, wherein different frequency resolutions are used for a first selected chirp BW and for a second selected chirp BW.