Abstract: A physical layer (PHY) preamble of a PHY data unit is generated, including generating one or more short orthogonal frequency division multiplexing (OFDM) symbols for one or more long training fields of the PHY preamble. Each of the one or more short OFDM symbols corresponds to a frequency domain sequence having a number of tones. Every N-th tone is modulated and tones between modulated tones are zero tones, where N is a positive integer greater than one. A time duration of each short OFDM symbol is 1/N of a time duration of a full inverse discrete Fourier transform (IDFT) of the frequency domain sequence. A data portion of the PHY data unit is generated, including generating one or more long OFDM symbols. A time duration of each long OFDM symbol is greater than a time duration of each of the one or more short OFDM symbols.

Abstract: An embedded continuity test circuit is provided. An integrated circuit includes a bond pad and an oscillator circuit. The oscillator circuit is configured to generate an oscillator signal having a first frequency when the bond pad is coupled to a bond region of a package and a second frequency when the bond pad is not coupled to the bond region of the package.

Abstract: The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

Abstract: A method for multi-phase high conversion ratio Switched Capacitor Power Conversion includes sequentially forming one of four subcircuits during a respective timing phase, wherein each subcircuit comprises at most three capacitors. Conversion between an input voltage of an input and an output voltage of an output occurs by sequentially connecting for each respective timing phase, one of the input, the output, a ground, a top plate of a first one of the three capacitors and a bottom plate of the first one of the three capacitors to one of a top plate of a second one of the three capacitors and a bottom plate of the second one of the three capacitors.

Abstract: Disclosed are switched-mode DC-DC power converter modules, SMPC controllers, and distributed-control multiphase SMPC systems. The controller comprises: a reference clock; a synchronisation input configured to receive a first synchronisation signal; a synchronisation output configured to transmit a second synchronisation signal; a control unit configured to control the operation of the SMPC module with a phase determined by the reference clock signal or the first synchronisation signal; a delay line configured to generate the second synchronisation signal by adding a delay to the selected one of the first synchronisation signal and the reference clock signal; a fault detection terminal; a memory configured to store a datum corresponding to a number N of SMPCs in the system; and a delay calculation module configured to calculate the delay in dependence on the datum and the signal at the fault-detection terminal. Associated methods are also disclosed.

Abstract: A method and apparatus for acquiring chirp data in a frequency modulated continuous wave (FMCW) radar system of a road vehicle. The method includes transmitting a FMCW signal comprising a plurality of ramping regions in which a frequency of the FMCW signal ramps up to a first frequency or ramps down to a second frequency. The method also includes receiving a reflected signal corresponding to the reflection of the FMCW signal from one or more physical objects. The reflected signal includes a plurality of ramping regions corresponding to the ramping regions of the transmitted FMCW signal. The method further includes sampling the reflected signal by: taking a plurality of samples in a ramping region in which the frequency of the reflected signal ramps up; and taking a plurality of samples in a ramping region in which the frequency of the reflected signal ramps down.

Abstract: A capacitive sampling circuit comprises: a first-differential-input-terminal, configured to receive a first one of a pair of differential-input-signals; a second-differential-input-terminal, configured to receive the other one of the pair of differential-input-signals; a capacitive-circuit-output-terminal, configured to provide a sampled-output-signal; a plurality of first-sampling-capacitors, each having a first-plate and a second-plate; a plurality of reference-voltage-terminals, each configured to receive a respective reference-voltage; and a first-capacitor-first-plate-switching-block configured to selectively connect the first-plate of each of the plurality of first-sampling-capacitors to either: (i) the first-differential-input-terminal; or (ii) a respective one of the plurality of reference-voltage-terminals; and a first-capacitor-second-plate-switch, configured to selectively connect or disconnect the second-plate of each of the plurality of first-sampling-capacitors to the second-differential-input-t

Abstract: An integrated circuit includes a voltage reference circuit including a Zener diode having a first terminal coupled to a first node and a second terminal coupled to a first voltage supply terminal. A proportional to absolute temperature (PTAT) circuit is coupled at the first node and configured to generate a PTAT current. A PTAT compensation circuit is coupled at the first node. The PTAT compensation circuit includes a first current mirror having a first branch coupled at the first node.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract: A built-in self-test, BIST, radar unit (100) is described. The BIST radar unit (100) comprises: a frequency generation circuit (110) configured to generate a mmW transmit signal; a transmitter circuit comprising: at least one phase shifter (130, 132) configured apply at least one phase shift to the mmW transmit signal; and at least one phase inverter (140, 142) coupled to the at least one phase shifter (130, 132) and configured to invert a phase of the phase shifted mmW transmit signal. A receiver configured to receive and process a received version of the mmW transmit signal.

Abstract: A semiconductor device including scan configuration circuitry that reconfigures latches of the device into a scan chain in response to assertion of a scan enable control signal, and scan control circuitry including delay circuitry, scan enable circuitry, evaluation circuitry, and scan reset circuitry. The scan reset circuitry keeps each of the secure latches in a predetermined reset state until assertion of both an evaluation signal and a scan mode signal. The delay circuitry includes N series-coupled flip-flops selected from different cell libraries detecting assertion of the scan mode signal and asserting a delay output signal only after N transitions of a test clock. The scan enable circuitry asserts the scan enable control signal when a scan enable command signal and the delay output signal are both asserted. The evaluation circuitry asserts the evaluation signal only when a collective state of the delay circuitry has achieved a predetermined state.

Abstract: A system includes a power transistor having a first drain connected to a load, a first gate connected to a gate driver, wherein the gate driver is configured to drive a first gate voltage on the first gate, and a first source connected to a ground. A sampling transistor includes a second drain connected to the first gate, a second gate connected to the first drain and a second source. A sampling capacitor is connected between the second source and the ground, wherein the sampling transistor is configured to sample a Miller plateau voltage of the first gate voltage on the sampling capacitor, in response to the first gate voltage increasing to the Miller plateau voltage and a first drain voltage of the first drain decreasing to a value equal to the Miller plateau voltage plus a threshold voltage of the sampling transistor.

Abstract: Embodiments are directed to methods and apparatuses for wireless vehicular communications using different communications protocols. A method includes communicating wirelessly via first vehicular communications circuitry by using a first vehicular communications protocol in which respective messages are sent synchronously. The method further includes, as part of each transmitted message, including data which is consistent with another vehicular communications protocol in which messages are sent asynchronously on behalf of other vehicular communications circuits and which indicates to the other vehicular communications circuits a reservation time for ensuing message subframes.

Abstract: A wireless communication device comprising processor electronics configured to select a channel bonding mode from a plurality of channel bonding modes. Each of the plurality of channel bonding modes indicates at least two wireless communication channels and at least one of the plurality of channel bonding modes corresponds to a mode that indicates a punctured wireless communication channel. The processor electronics are further configured to generate a frame to be transmitted from the wireless communication device in accordance with the selected channel bonding mode. The frame includes a preamble portion and a data portion and the preamble portion includes a first preamble field that identifies the selected channel bonding mode. Transceiver electronics are configured to transmit the frame on the wireless communication channels indicated by the selected channel bonding mode identified in the first preamble field.

Abstract: Power amplifiers and related methods are disclosed having configurable switched mode operation in a high-power mode of operation and a low-power mode of operation. The power amplifiers have a first cascode amplifier coupled to receive a positive differential input and a second cascode amplifier coupled to receive a negative differential input. The first and second cascode amplifiers include output stages and first/second input stages. The first input stages and the second input stages are enabled in a high-power mode of operation. The first input stages are disabled and the second input stages are enabled during a low-power mode of operation. For further embodiments, a switchable clamp operates in the low-power mode to clamp a voltage output for the second input stages. For further embodiments, the output stages are provided a variable voltage bias or are coupled to tunable capacitances that are varied between the low-power and high-power modes.

Abstract: A method for rate adaptation in a communication device includes, during a time interval, transmitting over a wireless channel to a peer communication device both (i) communication packets that carry user data, at a communication data rate, and (ii) channel-probing packets for probing channel conditions, at a channel-probing data rate that is derived from the communication data rate. A first statistical performance of the communication packets, and a second statistical performance of the channel-probing packets, are estimated over the time interval. The communication data rate is set for a subsequent time interval based on at least one of the first statistical performance and the second statistical performance.

Abstract: Embodiments of an RF amplifier include a transistor with a control terminal and first and second current carrying terminals, and a shunt circuit coupled between the first current carrying terminal and a ground reference node. The shunt circuit is an output pre-match impedance conditioning shunt circuit, which includes a first shunt inductance, a second shunt inductance, and a shunt capacitor coupled in series. The first shunt inductance comprises a plurality of bondwires coupled between the first current carrying terminal and the second shunt inductance, and the second shunt inductance comprises an integrated inductor coupled between the first shunt inductance and a first terminal of the shunt capacitor. The shunt capacitor is configured to provide capacitive harmonic control of an output of the transistor.

Abstract: An integrated circuit (IC) has scan chains of stitched registers that support scan testing of functional logic. The scan testing has a shift phase in which incoming and outgoing data are shifted into and out of the registers using a slow clock and a capture phase in which outgoing data from the functional logic is captured by the registers using launch-and-capture pulses of a fast clock to check for delay faults. During a warm-up period after termination of the slow clock but before application of the launch-and-capture pulses, the registers propagate data through their master latches without affecting the data stored in their slave latches. A warm-up controller configures the registers and generates control signals to perform either launch-on-shift or launch-on-capture scan testing. The flow of data and the warm-up controller operations keep the power supply rail voltage sufficiently charged for the fast launch-and-capture pulses.

Abstract: A cache is shared by a first and second processor, and is divided into a first cache portion corresponding to a first requestor identifier (ID) and a second cache portion corresponding to a second requestor ID. The first cache portion is accessed in response to memory access requests associated with the first requestor ID, and the second cache portion is accessed in response to memory access requests associated with the second requestor ID. A memory controller communicates with a shared memory, which is a backing store for the cache. A corresponding requestor ID is received with each memory access request. Each memory access request includes a corresponding access address identifying a memory location in the shared memory and a corresponding index portion, wherein each corresponding index portion selects a set in a selected cache portion of the first and second cache portions selected based on the received corresponding requestor ID.

Abstract: A defrosting system includes an RF signal source, one or more electrodes proximate to a cavity within which a load to be defrosted is positioned, a transmission path between the RF signal source and the electrode(s), and an impedance matching network electrically coupled along the transmission path between the RF signal source output and the electrode(s). A system controller is configured to modify, based on the reflected signal power, values of variable passive components of the impedance matching network to reduce the reflected signal power. The system controller may be configured to estimate the mass of the load by comparing component value(s) of one or more variable passive components of the impedance matching network with a component value table stored in memory, where stored mass values correspond to the stored component values. Desired signal parameters for the RF signal may be determined based on the estimated mass of the load.