Patents Assigned to NXP
-
Patent number: 10979033Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.Type: GrantFiled: July 27, 2020Date of Patent: April 13, 2021Assignee: NXP USA, Inc.Inventors: Andre Luis Vilas Boas, Felipe Ricardo Clayton
-
Patent number: 10976351Abstract: One example discloses a current monitoring device, including: a sense impedance configured to receive a current to be monitored; an impedance divider, coupled to the sense impedance, and configured to convert the current to be monitored to a differential voltage to be monitored; a reference circuit configured to generate a differential reference voltage; a comparator coupled to the impedance divider and the reference circuit and configured to output a signal if the differential voltage to be monitored is different than the differential reference voltage; and wherein the reference circuit includes a comparator trimming circuit configured to vary the differential reference voltage to compensate for offset biases in the comparator.Type: GrantFiled: February 12, 2019Date of Patent: April 13, 2021Assignee: NXP B.V.Inventors: Xu Zhang, Siamak Delshadpour, Ahmad Yazdi
-
Patent number: 10979543Abstract: Embodiments described herein provides a system for detecting data received in a low power low rate (LPMR) data frame format. The system includes a receiver and control circuitry. The receiver is configured to receive a data frame comprising an LPLR preamble portion and an LPLR data portion following the LPLR preamble portion. The LPLR preamble portion and the LPLR data portion occupy a bandwidth that is less than an allowed bandwidth. The control circuitry is configured to determine a mode of the data frame based on whether the data frame has an additional portion, and detect data field in the LPLR preamble portion from the data frame based on the mode of the data frame.Type: GrantFiled: December 19, 2018Date of Patent: April 13, 2021Assignee: NXP USA, INC.Inventors: Yakun Sun, Hongyuan Zhang, Lei Wang, Hui-Ling Lou
-
Patent number: 10979198Abstract: A communication device receives a first physical layer (PHY) data unit via a communication channel. The first PHY data unit corresponds to a trigger frame, and includes: a first PHY preamble having a legacy portion and a non-legacy portion, a first training field that includes a first training signal having a periodicity LP, and a second training field that includes a second training signal having the periodicity LP. The communication device generates a second PHY data unit. The second PHY data unit includes: a second PHY preamble that includes a third training field that includes a third training signal, and a fourth training field that includes a fourth training signal having a periodicity 2*LP. Generating the second PHY data unit comprises: modulating the third training field using a first tone spacing LTS between adjacent OFDM tones, and modulating the fourth training field using a second tone spacing equal to LTS/4 between adjacent OFDM tones.Type: GrantFiled: October 21, 2019Date of Patent: April 13, 2021Assignee: NXP USA, INC.Inventors: Yakun Sun, Hongyuan Zhang
-
Patent number: 10978791Abstract: One example discloses a combination antenna, including a near-field antenna, having a first portion and a second portion; and a far-field antenna, having a cavity; wherein the first portion of the near-field antenna structure is inside the cavity and the second portion is outside of the cavity.Type: GrantFiled: May 7, 2018Date of Patent: April 13, 2021Assignee: NXP B.V.Inventors: Liesbeth Gommé, Anthony Kerselaers
-
Patent number: 10979412Abstract: The present disclosure describes apparatuses and techniques for secure device authentication. In some aspects, a public ephemeral key of a device is exposed. A message received from a remote device to authenticate includes a hash of the public ephemeral key of the device, a public ephemeral key and an encrypted public key of the remote device, and an encrypted hash value useful to prove ownership of the public key received from the remote device. An encryption key is generated based on the public ephemeral key of the remote device and a private ephemeral key of the device. The device then decrypts, with the encryption key, the encrypted public key of the remote device and the encrypted hash value. The remote device is then authenticated by verifying, based on the decrypted hash value, that the remote device owns the decrypted public key.Type: GrantFiled: February 22, 2017Date of Patent: April 13, 2021Assignee: NXP USA, Inc.Inventor: Paul A. Lambert
-
Patent number: 10978444Abstract: A protection circuit including a low-leakage electrostatic discharge (ESD) protection circuit and at least one bracing circuit, the at least one bracing circuit including an RC input stage connected between a pad and ground, a driver transistor configured to drive a plurality of components of the at least one bracing circuit, a series transistor on an input line configured to act as a high impedance element during an ESD event, and a mini-clamp configured to short the input line to ground to protect a circuit to be protected during an ESD event.Type: GrantFiled: September 19, 2018Date of Patent: April 13, 2021Assignee: NXP B.V.Inventor: Gijs Jan de Raad
-
Patent number: 10978123Abstract: A data system includes an information bus, a volatile memory located on the information bus, and an MRAM located on the information bus. The data system includes threat detection circuitry. In response to a threat condition to the MRAM, data is transferred via the information bus from the MRAM to the volatile memory for storage during a threat to the MRAM as indicated by the threat condition. In some examples, the threat condition is characterized as a magnetic field exposure.Type: GrantFiled: December 4, 2018Date of Patent: April 13, 2021Assignee: NXP USA, Inc.Inventors: Geoffrey Mark Lees, Lawrence Loren Case, Nihaar N. Mahatme, Jeffrey C. Cunningham
-
Patent number: 10972096Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.Type: GrantFiled: June 28, 2019Date of Patent: April 6, 2021Assignee: NXP USA, INC.Inventors: Robert Matthew Mertens, James Robert Feddeler, Michael A. Stockinger
-
Patent number: 10972002Abstract: A regulator clamp circuit includes a comparison circuit having a sample and hold circuit. The comparison circuit compares a regulated voltage with a sampled voltage of the regulated voltage from a previous time. In some embodiments, the sampled voltage can be determined during a sampling phase that occurs prior to a clamp regulation phase. During the clamp regulation phase, the comparison circuit compares the regulated voltage with the sampled voltage and outputs a signal to activate an actuator circuit to clamp the regulated voltage when the regulated voltage terminal has a higher amount of charge than desired.Type: GrantFiled: May 21, 2020Date of Patent: April 6, 2021Assignee: NXP USA, INC.Inventors: Marcos Mauricio Pelicia, Luis Enrique Del Castillo, Eduardo Ribeiro da Silva, Ivan Carlos Ribeiro do Nascimento
-
Patent number: 10969457Abstract: A receiver-system comprising a path-switching-unit, a redirect-switching-unit, a plurality of receive-paths, and a processor. The path-switching-unit has a plurality of path-switch-input-terminals that are each couplable to a receive-antenna. The redirect-switching-unit has a plurality of redirect-switch-output-terminals that are each associated with one of the plurality of path-switch-input-terminals in order to define a plurality of switch-terminal-pairs. The receive-paths are connected between a path-switch-output-terminal and a redirect-switch-input-terminal. The path-switching-unit and the redirect-switching-unit are configured to selectively connect each receive-path between different ones of the plurality of switch-terminal-pairs, based on a switch-control-signal.Type: GrantFiled: December 1, 2018Date of Patent: April 6, 2021Assignee: NXP B.V.Inventors: Olivier Jamin, Anton Salfelner
-
Patent number: 10972054Abstract: Embodiments of systems and method for automatically biasing power amplifiers using a controllable current source are disclosed. In an embodiment, a bias controller for a power amplifier includes a first reference device source/drain interface, a first controllable current source configured to generate a first reference current in response to a first current control signal and to provide the first reference current to the first reference device source/drain interface, a first reference device gate interface, a first current-to-voltage controller configured to generate a first stabilized voltage in response to the first reference current and to provide the first stabilized voltage to the first reference device gate interface, and a first power amplifier (PA) interface configured to output a first control voltage in response to the first stabilized voltage.Type: GrantFiled: May 10, 2019Date of Patent: April 6, 2021Assignee: NXP USA, Inc.Inventors: Elie A. Maalouf, Xu Jason Ma
-
Patent number: 10972196Abstract: A first communication device generates and transmits a first trigger frame. One or more trigger type information fields of the first trigger frame are set to a first one or more respective values that indicates the first trigger frame is for: i) a multi-user (MU) ranging measurement procedure, and ii) causing multiple second communication devices to simultaneously transmit first null data packets (NDPs) as part of a first MU transmission associated with the MU ranging measurement procedure. The first communication device generates and transmits a second trigger frame. One or more trigger type information fields of the second trigger frame are set to a second one or more respective values that indicates the second trigger frame is for i) an MU ranging measurement procedure, and ii) causing the multiple second communication devices to simultaneously transmit feedback packets to the first communication device as part of a second MU transmission associated with the MU ranging measurement procedure.Type: GrantFiled: July 24, 2018Date of Patent: April 6, 2021Assignee: NXP USA, INC.Inventors: Liwen Chu, Christian R. Berger, Niranjan Grandhe, Hongyuan Zhang, Hui-Ling Lou
-
Patent number: 10971613Abstract: A semiconductor device includes a base substrate, a doped region at an upper surface of the base substrate, and a transistor over the upper surface of the base substrate and formed from a plurality of epitaxially-grown semiconductor layers. The doped region includes one or more ion species, and has a lower boundary above a lower surface of the base substrate. The base substrate may be a silicon substrate, and the transistor may be a GaN HEMT formed from a plurality of heteroepitaxial layers that include aluminum nitride and/or aluminum gallium nitride. The doped region may be a diffusion barrier region and/or an enhanced resistivity region. The ion species may be selected from phosphorus, arsenic, antimony, bismuth, argon, helium, nitrogen, and oxygen. When the ion species includes oxygen, the doped region may include a silicon dioxide layer formed from annealing the doped region after introduction of the oxygen.Type: GrantFiled: March 30, 2020Date of Patent: April 6, 2021Assignee: NXP USA, Inc.Inventors: Yuanzheng Yue, David Cobb Burdeaux, Jenn Hwa Huang, Bruce McRae Green, James Allen Teplik
-
Patent number: 10972142Abstract: Wireless networking transceiver circuitry for an integrated circuit device includes a plurality of wireless networking transceiver subsystems, each subsystem including respective processing circuitry configurable for coupling to radio circuitry to implement a respective set of protocol features selected from at least one overall set of protocol features. Memory circuitry is provided, sufficient to support a respective set of protocol features in each subsystem when at least one respective set of protocol features is smaller than the overall set of protocol features. Memory-sharing circuitry is provided, configurable to couple respective portions of the memory circuitry to the processing circuitry of respective subsystems. The memory circuitry and the memory-sharing circuitry may be outside the subsystems, or distributed within the subsystems. The memory may be 60% of an amount of memory sufficient to support the overall set of protocol features in all subsystems.Type: GrantFiled: December 5, 2019Date of Patent: April 6, 2021Assignee: NXP USA, Inc.Inventors: Timothy J. Donovan, Yui Lin, Lite Lo, Zhengqiang Huang
-
Patent number: 10972091Abstract: Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack.Type: GrantFiled: December 3, 2019Date of Patent: April 6, 2021Assignee: NXP USA, Inc.Inventor: Venkata Naga Koushik Malladi
-
Patent number: 10963036Abstract: Systems and method for idle loop detection and control are disclosed. A processor operates in operating modes including an active mode and a disabled mode, and an interconnect bus is coupled between the processor and one or more additional electronic circuits. Logic within the processor is coupled to snoop the interconnect bus, and the logic is programmed to detect a new idle loop based upon repeated instructions on the interconnect bus and to place the processor in the disabled mode based upon execution of the new idle loop, which represents a previously unknown idle loop for the processor. Further, the logic can be programmed to store state data for the processor when the new idle loop is detected, and the logic can also be programmed to place the processor in the active mode based upon detection of a wakeup event for the new idle loop on the interconnect bus.Type: GrantFiled: April 16, 2018Date of Patent: March 30, 2021Assignee: NXP USA, Inc.Inventors: Ashish Mathur, Sandeep Jain
-
Patent number: 10966280Abstract: A first communication device generates a media access control (MAC) protocol data unit (MPDU) delimiter having i) a feedback indication field and ii) a feedback content field. The feedback indication field is generated to include a first value that indicates the MPDU delimiter includes the feedback content field rather than an MPDU length field corresponding to a second value of the feedback indication field. The feedback content field is generated to include feedback information such as acknowledgement information regarding a communication frame previously transmitted by a second communication device, or control, management, and/or status information regarding the first communication device that was previously requested by the second communication device. The first communication device then transmits a packet that includes the MPDU delimiter to the second communication device.Type: GrantFiled: September 13, 2019Date of Patent: March 30, 2021Assignee: NXP USA, Inc.Inventors: Liwen Chu, Hongyuan Zhang, Hui-Ling Lou
-
Patent number: 10965346Abstract: A near-field device, including: a near-field receiver coupled to a near-field receiver antenna and a decoder circuit; wherein the near-field receiver antenna is configured to be capacitively coupled at a first location on a conductive structure; wherein the near-field receiver antenna is configured to receive a near-field signal from the conductive structure through the receiver's capacitive coupling; and wherein the decoder circuit is configured to detect variations in the near-field signal.Type: GrantFiled: May 23, 2017Date of Patent: March 30, 2021Assignee: NXP B.V.Inventors: Anthony Kerselaers, Pieter Verschueren
-
Patent number: 10964332Abstract: An apparatus and method for speech communication is described. An audio transmit processor captures at least two audio signals from an audio source, and processes the at least two audio signals to provide a mono audio signal and a non-audio signal comprising spatial information representative of the direction of the audio source. The audio transmit processor combines the non-audio signal with the mono audio signal by watermarking; and transmits the watermarked audio signal. An audio receive processor receives a watermarked audio signal and extracts a mono audio signal and a non-audio signal comprising spatial information from the watermarked audio signal. The audio receive processor processes the mono audio signal and spatial information to generate at least two output audio signals.Type: GrantFiled: September 20, 2017Date of Patent: March 30, 2021Assignee: NXP B.V.Inventor: Temujin Gautama