Abstract: A contactless communication device includes a near field communication (NFC) module for generating an electromagnetic carrier signal and modulating the carrier signal according to data to be transmitted, and an antenna coupled to and driven by said NFC module with the modulated carrier signal. The device includes an RF front end coupled between said NFC module and said antenna and further includes a detection module coupled to said NFC module for detecting an end of a PauseA of an incoming RF signal by monitoring an amplitude of a digital output signal derived from the incoming RF signal. The detection module detects the PauseA in said digital output signal by comparing the amplitude of said output digital signal to a first level. The detection module further detects the end of the PauseA in said digital output signal by comparing the amplitude of said digital output signal to a second level.

Abstract: A system, method, apparatus and electronic control unit are provided for centralized data collection at a single controller device (110) in a distributed service-oriented system (100) by applying one or more classifiers (102-104, 114) to a message traffic packet (1) received at the Ethernet switch (101) of the single controller device to selectively identify service update information from service-oriented traffic messages in the message traffic packet without generating additional message traffic packets on the network system bus, and by mirroring each message traffic packet (3) containing service update information to a processing element (111) in the single controller to identify and extract specified data from the identified service update information for storage in a centralized database which is updated as services publish new information on the network system bus.

Abstract: Embodiments of an authentication system and a method for authentication using ciphers are described. In the system and method, cryptographic calculations of an encryption algorithm are executed at a base station, in a determined secure environment, to produce a pre-calculated cipher for a subsequent authentication process. The pre-calculated cipher is then used to transmit an authentication request message from the base station and validation of an authentication response message for the subsequent authentication.

Abstract: Flexible structured-pipelined CORDIC techniques efficiently perform various CORDIC operations and support different parameters for MIMO MEQ processing. The structured-pipelined CORDIC techniques simplify signal processing flow, unify input requirements and output delay, and simplify integration. Look-up table techniques provide quick generation of control signals, reduce design and verification efforts, and facilitate design automation. In addition, the structured-pipelined CORDIC techniques are conducive to hardware sharing and reuse. The structured-pipelined CORDIC techniques reduce integrated circuit area and power consumption.

Abstract: A clock glitch alerting circuit is configured to detect a glitch in an input clock signal, and activate and provide an alert signal to a security controller when the glitch is detected. The clock glitch alerting circuit is further configured to delay the input clock signal based on multiple selection signals, and provide one of a delayed clock output signal and a filtered clock output signal to the security controller based on the alert signal. The clock glitch alerting circuit is further configured to generate and provide a count value to the security controller that indicates a time duration available by the security controller to execute a security critical operation after receiving the activated alert signal.

Abstract: An embodiment of a semiconductor device may include a semiconductor substrate, a first semiconductor region comprising a first material with a first polarity formed within the semiconductor substrate and a second semiconductor region comprising the first material with a second polarity formed within the semiconductor substrate and coupled to the first semiconductor region. In an embodiment, a semiconductor device may also include a first electrode coupled to the first semiconductor region, a second electrode coupled to the second semiconductor region, and a depletion region formed between the first semiconductor region and the second semiconductor region. The depletion region may include a mixed crystal region that includes a mixed crystal alloy of the first material and a second material, wherein the mixed crystal region has a lower bandgap energy than a bandgap energy of the first material.

Abstract: A vehicle communication system includes a vehicle access module, a plurality of cables coupled to the vehicle access module, and an antenna coupled to the plurality of cables, wherein based upon short circuit analysis of the plurality of cables by the vehicle access module, the plurality of cables are decoupled from the vehicle access module. In order to determine with a short circuit exists in the plurality of cables, the short circuit analysis includes a determination as to whether a maximum of antenna current samples taken from the antenna is greater than a diagnostic parameter times an average of the antenna current samples.

Abstract: A security system for vetting run-time operation of device hardware. A model stores vetted states based on device hardware security signals, a severity level value and at least one vetted next state. The vetting system compares each state of the device hardware with the vetted next states of a current state, and provides an indication and a severity level when the real next state does not match a vetted next state. In response to the indication, the synchronization system performs synchronization by comparing each subsequent real next state of the device hardware with the vetted states until initial synchronization occurs when any subsequent real next state matches a vetted state. The learning system receives feedback from the device hardware in response to the indication, and when indicated by the feedback, updates the model in accordance with the feedback.

Abstract: Embodiments are provided herein for a substrate having one or more embedded traces and a method for fabricating one or more embedded traces. The method includes: forming a bump on a first major surface of a substrate, the bump having a height measured from the first major surface to a top surface of the bump; forming a trace comprising: a lower trace portion that directly contacts the first major surface, a sidewall trace portion that directly contacts at least one sidewall of the bump, and an upper trace portion that directly contacts the top surface of the bump; depositing a blanket dielectric layer over the trace; and etching away a top portion of the blanket dielectric layer to expose a top surface of the upper trace portion.

Abstract: A high-voltage automotive battery pack, system, architecture, and methodology include a first and second adjacent battery cells (410, 420) connected to a dual-cell supervisor circuit (412) that is positioned to bridge the first and second battery cells and that is connected to monitor the first and second battery cells, wherein the dual-cell supervisor circuit comprises current injection and impedance-detection circuitry (510) for separately measuring a voltage, impedance, and temperature at each of the first and second battery cells, alone or in combination with an external switched inductor (501) which is coupled to be switched across the first battery cell (505) or the second battery cell (506) to perform low-loss impedance measurement of the first and second battery cells.

Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die.

Abstract: A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.

Abstract: A frequency reference generator includes (i) an integrated frequency source having drive circuitry that drives a resonant (e.g., non-trimmable LC) tank to generate an oscillator signal, (ii) at least one temperature sensor that generates at least one measured temperature signal, and (iii) a frequency-adjustment circuit that adjusts the oscillator signal frequency to generate the frequency reference based on the measured temperature signal and a (e.g., sample-specific) mapping from temperature to a corresponding frequency-adjustment parameter (e.g., a divisor value for a fractional frequency divider). In some embodiments, a Colpitts oscillator generates the oscillator signal based on the measured temperature signal, where the Colpitts oscillator has voltage/temperature-compensation circuitry that compensates for variations in power supply voltage and operating temperature. Such frequency reference generators achieve substantial PVT insensitivity with as little as a single 1T-trim or even no trim at all.

Abstract: A circuit (200) for testing failure of a connection between a radio frequency, RF, integrated circuit (201) and external circuitry (204), the circuit comprising: an amplifier (205) having first and second input paths (215, 216) and first and second output paths (206, 207); a first power detector (208, 209) coupled to one of said first or second output paths; at least one connection (211) between said first and second output paths (206, 207) and said external circuitry (204), connecting said outputs to a RF combiner (210) said external circuitry; at least one disabling circuit (230, 232, 234, 236, 240, 242, 260, 262) coupled to at least one of said first and second output paths (206, 207) or at least one of said first and second input path (215, 216), before said path reaches said power detector (208, 209); for disabling one of said inputs or outputs; wherein when said input or output path is disabled (206, 207), and a signal is output along the enabled output path (206, 207), the power detector (208, 209) on

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), at least one conversion circuit, and at least one amplifier such that a number of conversion circuits and a number of amplifiers is less than a number of DACs. Each DAC is configured to receive an analog input signal in non-overlapping durations of a clock signal and generate a corresponding analog output signal. At least one of the conversion circuits is coupled with at least two DACs, and each conversion circuit is configured to perform conversion operation on a corresponding analog output signal to generate digital signals. At least one of the amplifiers is coupled with at least two DACs, and each amplifier is configured to perform amplification operation on a corresponding analog output signal.

Abstract: A method and apparatus for updating an encryption key for performing encrypted communication over a communications network. The method comprises, within a timestamp distribution node, transmitting a message to at least one timestamp reception node of the communications network containing a timestamp value. The method further comprises, within the at least one timestamp reception node, receiving the message from the timestamp distribution node and extracting the timestamp value. Wherein, within each of the timestamp distribution node and the at least one timestamp reception node, the method comprises generating at least one updated encryption key for performing encrypted communication based at least partly on the extracted timestamp value.

Abstract: A semiconductor device includes a semiconductor substrate with a collector region formed within the semiconductor substrate. A base region, including a first base region and a second base region, is formed over the collector region. An extrinsic base region is formed laterally adjacent to and coupled to the second base region. A base link region is disposed proximate to the second base region, wherein the base link region couples the extrinsic base sidewall to the second base region. A method for forming a semiconductor device includes forming the collector region within the semiconductor substrate, forming a plurality of dielectric layers over the collector region, forming an extrinsic base layer over the collector region, etching an emitter window, forming the first base region over the collector region, forming the second base region over the first base region, wherein forming the second base region includes forming the base link region.

Abstract: A system, method, apparatus and integrated circuit are provided for collecting runtime performance data with a set of hardware timers under control of a dedicated hardware control register by connecting a central processing unit (CPU) and memory to a timer block bank having a plurality of timer instances which are selectively enabled and activated to collect runtime performance data during execution of application code by measuring specified software execution events, where the dedicated hardware control register includes a plurality of register fields for independently controlling activation behavior of the plurality of timer instances in response to a single write operation to all register fields in the hardware control register.

Abstract: Systems and methods for protocol-tolerant communications in a Controller Area Network (CAN) are described. In some embodiments, a method may include receiving a frame at a network node; identifying, by the network node, a bit in a selected field of the frame; and determining, by the network node, that the frame follows a second format despite the bit indicating that the frame follows a first format. In other embodiments, a CAN controller includes message processing circuitry; and a memory coupled to the message processing circuitry, the memory having program instructions that configure the message processing circuit to: receive a frame; identify a bit in a selected field of the frame; and determine that the frame follows a Classical CAN format despite the bit indicating that the frame follows a flexible data-rate CAN (CAN FD) format.