Abstract: Disclosed is a battery charger including a battery cell, a reference voltage generating section, an A/D converting section including an A/D converter and a control section. The reference voltage generating section includes a first reference voltage circuit generating a first reference voltage and a second reference voltage circuit generating a second reference voltage equal to the first reference voltage. To diagnose the A/D converter, the first reference voltage circuit is used. To diagnose the first reference voltage circuit, a second A/D conversion value obtained by A/D converting a second divided voltage of the second reference voltage via the A/D converter using the first reference voltage is compared with a first reference value obtained by A/D converting a first divided voltage of the first reference voltage via the A/D converter using the first reference voltage when the first reference voltage circuit is normal.

Abstract: An image processing system is provided. A region specifying component specifies one or more playing regions for generating predetermined sounds in an image represented by the moving image data that have been acquired by the acquiring component. A detecting component detects a specific image showing a specific subject existing in the image represented by the moving image data that have been acquired by the acquiring component. An assigning component assigns, for each of the playing regions that have been specified by the region specifying component, sounds to be outputted in a case where the specific image that has been detected by the detecting component overlaps those playing regions. A signal outputting component outputs signals representing the sounds that have been assigned to those playing regions by the assigning component, in a case where the specific image overlaps the playing regions.

Abstract: A driving circuit includes a pair of operational amplifiers, one producing an analog voltage output of positive polarity, the other producing an analog voltage output of negative polarity. An output switching circuit interchanges these outputs between a pair of data lines. One or both of the operational amplifiers includes a parasitic diode having one terminal connected to the output terminal of the operational amplifier and another terminal normally connected to a power supply voltage of the operational amplifier. When the output of the operational amplifier is switched, a protective switching circuit temporarily disconnects the parasitic diode from the power supply of the operational amplifier and instead connects it to a power supply line carrying a voltage high enough, or low enough, to ensure that the parasitic diode is not forward biased by the existing voltage on the data line to which the output is switched.

Abstract: Disclosed is a plating method including: performing plating on a plating surface of a plating substrate with a cathode electrode contacting an area in an outer circumferential section of the plating substrate where the cathode electrode is to be contacted, the plating substrate being provided with a dummy plating area between the area where the cathode electrode is to be contacted and a product area on the plating surface of the plating substrate, by supplying a plating solution to the plating surface of the plating substrate and applying electric current between the cathode electrode and an anode electrode via the plating solution.

Abstract: There is provided a non-volatile storage device including: a memory array section arrayed with plural non-volatile memory cells for electronically writable data storage; plural bit lines that are connected to respective memory cells and have voltage levels that change according to the data stored in the memory cells; a supply section that supplies a voltage of a reference level to act as a comparator reference when determining data stored in the memory cells; a comparator section that compares the voltage level of the bit line connected to the memory cell subject to reading against the reference level supplied by the supply section; and a charging section that, in preparation for comparison by the comparator section, charges the bit line connected to the memory cell subject to reading to the voltage of the reference level supplied by the supply section.

Abstract: An apparatus for generating a layout pattern of each element includes a storage, a basic figure generator, an additional figure generator, a display unit and an operation input unit; wherein the storage stores terminal figure relative position information, figure adjustment value information and additional figure relative position information; the basic figure generator generates an effective area figure and a terminal figure of a layout pattern generation target element on the basis of the terminal figure relative position information and the figure adjustment value information; the additional figure generator generates the additional figure of the layout pattern generation target element on the basis of the generated effective area figure and terminal figure and the additional figure relative position information; the display unit displays the generated effective area figure, terminal figure and additional figure; and the figure adjustment value information is changed depending on an input from the operatio

Abstract: A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines.

Abstract: A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal

Abstract: A semiconductor device capable of achieving desirable communication behavior through a bus regardless of whether or not a pull-up resistor is connected on a bus line. The semiconductor device includes external pull-up determination unit and internal pull-up setting unit. The external pull-up determination unit applies a pull-down voltage through an internal pull-down resistor to the bus line, and determines whether an external pull-up resistor external to the semiconductor device is connected on the bus line on the basis of the voltage level of the bus line when the pull-down voltage is applied to the bus line. The internal pull-up setting unit stops application of the pull-down voltage, and applies a pull-up voltage through an internal pull-up resistor to the bus line if it is determined that no external pull-up resistor is connected on the bus line.

Abstract: A method having the steps of applying the same gate voltage to each of gate terminals of a plurality of memory cells via word lines to designate the memory cells as a write target, and simultaneously applying a write voltage that corresponds to each write data across drain-source terminals of two or more memory cells that are write targets via bit lines to write simultaneously a plurality of data elements having mutually different data values to the memory cells.

Abstract: A semiconductor device has multiple high-side field-effect transistors and multiple low-side field-effect transistors connected to a single output terminal to generate an output signal. A driver circuit outputs driving signals that turn the field-effect transistors on and off. The driving signal for the field-effect transistors on each side is conducted by a salicided gate line with salicide block areas that produce successive delays, causing the field-effect transistors to turn on sequentially. Alternatively, the transistors have different threshold voltages, or the driving signals for different transistors are output from drivers with different driving abilities, again causing the transistors to turn on sequentially. The output signal therefore rises and falls gradually, reducing electromagnetic interference.

Abstract: There is provided a nonvolatile semiconductor memory wherein a normal mode voltage is provided to a selected word line when a normal mode is selected, and a test mode voltage lower than the normal mode voltage is provided to the selected word line when a test mode is selected, thus leakage current is detected by selecting the test mode.

Abstract: An MCP type semiconductor memory device having a defective cell remedy function, which enables easy design and manufacture while minimizing chip area increase, is provided. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions.

Abstract: Extracting information corresponding to a three-dimensional object from an image captured by plural imaging apparatuses is implemented with a simple configuration and a simple processing. Parallax information representing a parallax amount in the X direction of a pair of images captured by a pair of imaging apparatuses disposed at different horizontal positions is stored in a storage section 44, and a parallax correction control section 42 reads out a parallax amount corresponding to a Y coordinate value of image data for one line input from a pre-image processing unit 14 from the storage section 44 and outputs a selection signal to selectors 38 and 44 such that the output of one image data is delayed by the differential amount. A differential image generation unit 18 calculates an absolute value of the differential of the pair of input image data for each pixel and outputs the result as a differential image for detecting the three-dimensional object.

Abstract: An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate is provided, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip provided adjacent to the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip.

Abstract: A light amount measuring apparatus including a light amount measuring circuit and a power supply for supplying power to the light amount measuring circuit; wherein the light amount measuring circuit includes a light receiving device for receiving light and outputting an electric signal corresponding to light amount of the received light; a first switch for switching between electrical connection and disconnection between the light receiving device and the power supply; and a drive controller for controlling the first switch so that the first switch electrically connects the light receiving device to the power supply when the light receiving device is set to an activated state and electrically disconnects the light receiving device from the power supply when the light receiving device is set to a deactivated state.

Abstract: In a driving circuit of a display device, a period for writing to pixels is shortened while an increase in size of an integrated circuit is avoided. In a first period of the writing period, the pixel is charged up with a gradation potential of a particular node in a node group that includes a node which is at an objective gradation potential. In the first period, a plurality of lines corresponding to the number of nodes included in the node group are connected in parallel between the particular node and the pixel. In a second period of the data-writing period, this parallel connection is cancelled and only the node corresponding to the objective gradation potential is connected to the pixel.

Abstract: A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer.

Abstract: There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces.

Abstract: The light sensor according to an exemplary embodiment of the present invention is a multi-function light sensor that is equipped at low cost with both an ultraviolet light sensor and a visible light sensor and suppresses leak current between adjacent elements on the same substrate. The light sensor is equipped with a SOI substrate, formed from a silicon oxide insulating film and a silicon semiconductor layer made up from single crystal silicon, on a silicon substrate. Photodiodes PD1 and PD2 are formed on the silicon substrate, and a photodiode UV-PD, and main portions (source, drain and channel regions) of a MOSFET configuring a control circuit, are formed in the silicon semiconductor layer on the insulating film.