Abstract: A semiconductor device includes a semiconductor layer with an impurity of a first conductivity type diffused therein, and a local insulating layer, source layer, and a drain layer formed therein. The drain layer has an impurity of a second conductivity type opposite to the first conductivity type. A gate electrode is formed over the semiconductor layer extending from over the local insulating layer to the source layer. A low-concentration diffusion layer is formed in the semiconductor layer below the drain layer. First and second gate insulating films are formed between the gate electrode and the semiconductor layer, and respectively extending from an end, on the source layer side, of the gate electrode to the local insulating layer without reaching the local insulating layer, and extending from an end on another side of the local insulating layer to the source layer.

Abstract: A semiconductor method comprises a method for making a device comprising: a base; a semiconductor chip provided on the base which includes a first main surface 20a on which a plurality of electrode pads is provided, a surface protecting film provided on the first main surface, a second main surface which opposes the first main surface, and a plurality of side surfaces between the surface of the surface protecting film and the second main surface; an insulating extension portion formed so as to surround the side surfaces of the semiconductor chip; a plurality of wiring patterns electrically connected to the electrode pads, respectively and extended from the electrode pads to the surface of the extension portion; a sealing portion formed on the wiring patterns such that a part of each of the wiring patterns is exposed; and a plurality of external terminals provided on the wiring patterns in a region including the upper side of the extension portion.

Abstract: In order to provide a thin-film resistor and a manufacturing method thereof capable of restraining reduction of a Q-value of varactor by reducing a parasitic capacitance between the resistor and the substrate, the thin-film resistor includes a semiconductor substrate 10 including an integrated circuit 12 having a plurality of electrode pads 14 placed in a distance from each other in the most upper part of a plurality of stacked interconnections, and the integrated circuit 12 having a passivation film 16 formed between the plurality of electrode pads 14; a secondary interconnections 18 electrically connected to the electrode pads 14; an insulating film 20 formed in a place in between the secondary interconnections 18 on the passivation film 16; and a resistor 26 formed 18 in a predetermined place in between the secondary interconnections 18 on the insulating film 20.

Abstract: A semiconductor device includes JTAG ports receiving integrally command information representing a command and password information representing a password, a processor for performing a process in response to the command, an output port outputting consequence information representing a consequence of the process, a transfer section for transferring the command to the processor and for transferring the consequence information to the output port, and a cut off section. The cutoff section cuts off at least one of transferring the command information to the processor and transferring the consequence information to the output port when the password does not match a predetermined proper password. Thus, the semiconductor device can advantageously heighten its security effect.

Abstract: A circuit board has an embedded electronic component such as an integrated circuit chip with a wafer level chip size package. A via hole extends through the electronic component. Another via hole extends through the substrate or prepreg on which the electronic component is mounted inside the circuit board. Conductors in the via holes enable a terminal on the surface of the electronic component to be electrically connected to a wiring pattern or another electronic component on the opposite side of the substrate or prepreg. Routing the connection through the electronic component itself saves space and reduces the length of the connection.

Abstract: A source driver for a liquid crystal display (LCD) panel in which during a first predetermined period immediately after polarity of a voltage according to image data is inverted, each column terminal of the LCD panel is shorted to a common line through an output terminal and a second switch element, a first output amplifying portion is set to a high impedance state, and an output signal of a second output amplifying portion is fed back to a differential amplifying portion through a third switch element. During a period after the first predetermined period and before inversion of polarity of a voltage according to the image data, an output signal of the first output amplifying portion is supplied to the output terminal without passing though a switch element, and is fed back to the differential amplifying portion through a fourth switch element. The output signal of the second output amplifying portion is fed back to the differential amplifying portion through the first and fourth switch elements.

Abstract: A current fuse includes: a fuse portion that is disposed on a substrate; and a conductive portion that is placed in an overlying layer above the fuse portion or an underlying layer between the substrate and the fuse portion, has the same potential as that of one portion of the fuse portion when a current is passed through the fuse portion, and extends apart from the fuse portion from the one portion side of the fuse portion as far as an overlying layer above or an underlying layer below another portion of the fuse portion whose potential differs from that of the one portion.

Abstract: The present invention provides a transistor, a semiconductor device and a transistor fabrication process that thoroughly ameliorate electric fields in a transistor element. Namely, the transistor includes a semiconductor substrate, incline portions, a gate electrode, side walls, and a source and a drain. The semiconductor substrate includes a protrusion portion at a surface thereof. The incline portions constitute side surface portions of the protrusion portion and are inclined from the bottom to the top of the protrusion portion. The gate electrode is formed on the top of the protrusion portion, with a gate insulation film interposed therebelow. The side walls are formed on the top of the protrusion portion at two side surfaces of the gate electrode and the gate insulation film. The source and the drain each include a low density region and a high-density region.

Abstract: A semiconductor integrated circuit device of the invention can reduce a manufacturing cost and achieve size reduction without degrading performances. The semiconductor integrated circuit device includes an internal circuit and at least one input/output circuit. Each input/output circuit is adapted to feed an input signal from outside to the internal circuit and to output an output signal from the internal circuit to the outside. The semiconductor integrated circuit device also includes at least one first power source terminal. Each first power source terminal is associated with each input/output circuit for supplying a drive voltage to the internal circuit. The semiconductor integrated circuit device also includes at lease one second power source terminal. Each second power source terminal is associated with each input/output circuit for supplying a drive voltage to the associated input/output circuit. The semiconductor integrated circuit device also includes at least one common ground terminal.

Abstract: There is provided a method of fabricating an EEPROM for forming a memory cell transistor and a selection transistor, the method includes: forming a first source region and a first drain region of the memory cell transistor; forming a first gate oxide film; forming a resist having at least one through hole on the first gate oxide film; adding conductivity type impurities through the through hole; partially removing the first gate oxide film and forming a tunnel oxide film in a region corresponding to the through hole; forming a floating gate electrode and a second gate oxide film formed on the floating gate electrode; forming a control gate electrode and a selection transistor gate electrode on the second gate oxide film and at a region in which the selection transistor is formed; and forming a second source region and a second drain region of the selection transistor.

Abstract: A silicon carbide semiconductor device is fabricated by forming an amorphous layer in a semiconductor layer of a silicon carbide substrate at a boundary between a cell forming area and an outer peripheral area, forming an outer peripheral insulating film over the semiconductor layer in the outer peripheral area, and thermally oxidizing an upper surface of the semiconductor layer in the cell forming area and at least a portion of the amorphous layer exposed by the outer peripheral insulating film to form a gate oxide film including a stepped portion of increased thickness adjacent the outer peripheral insulating film. The gate electrode layer is then formed which extends from the gate oxide film to above the outer peripheral insulating film.

Abstract: A fast Fourier transform circuit includes a computation component, an extraction component and a setting component. The extraction component, at each step of the computation, extracts, from computation result data points calculated by the computation component, data in a pre-specified range with a number of bits the same as a predetermined number of bits, which is an effective range for a butterfly computations. The setting component sets the data points of the predetermined number of bits which have been extracted by the extraction component to serve as input data when butterfly computations of a next step are to be performed by the computation component.

Abstract: An element isolation film is formed by filling an oxide in a trench formed in an element isolation region of a semiconductor substrate to thereby form an insulation film for element isolation. A method of forming the element isolation film includes a first step of depositing a material in a plasma state including oxygen and silicon on an inner surface of the trench while applying no bias voltage (or a relatively low voltage), and a second step of filling the material in a plasma state including oxygen and silicon in the trench while applying a bias voltage (or a relatively high voltage).

Abstract: A semiconductor device is manufactured in a silicon-on-insulator (SOI) wafer having an silicon active layer, a buried oxide layer, and a supporting substrate layer. Before the wafer is diced into chips along scribe lines, the silicon active layer is selectively etched to form trenches surrounding the scribe lines. The wafer is then diced using a dicing apparatus having a blade width smaller than the width of the trenches. The dicing blade accordingly does not make contact with the silicon active layer, which is particularly vulnerable to chipping.

Abstract: A voltage output device which is capable of preventing an increase in circuit scale and includes an offset compensation function that is suitably applicable in particular to a drive circuit for display devices such as liquid crystal display panels. The voltage output device includes an operational amplifier which has an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal.

Abstract: A wafer holding apparatus for holding a wafer in a semiconductor fabrication apparatus includes a stage having a wafer receiving area with a large number of apertures. A gas, supply source supplies gas to the apertures to levitate the wafer by gas pressure. The levitated wafer is held in contact with a retainer disposed above a peripheral part of the wafer receiving area by the gas pressure, which the retainer resists. The wafer is thereby held securely even when the stage is moved, and the surface configuration of the wafer is not affected by the presence of foreign matter between the wafer and stage.

Abstract: An ASK modulator for reducing the difference in the On/Off ratio due to the difference in the envelope frequency components without deteriorating an adjacent wave leakage power is disclosed. The ASK modulator includes a Manchester encoder that generates Manchester-encoded signals by applying Manchester encoding to an input signal sequence, a waveform shaping unit that generates band-limited encoded signals from the Manchester-encoded signals, and detects and limits minimum values of waveforms of the band-limited encoded signals to generates shaped signals, and a modulating unit that modulates carrier waves based on the shaped signals.

Abstract: A semiconductor acceleration sensor includes an acceleration sensor chip that includes a weight portion, a base portion provided around the weight portion with a gap therebetween, and beam portions flexibly connecting the weight portion and the base portion; and a stopper plate that is provided above the acceleration sensor chip. The stopper plate includes: a plurality of fixing portions that are protrudingly provided at positions opposite to the base portion and are fixed to the base portion; first concave portions that are formed around the fixing portions at positions opposite to the weight portion and define the displacement of the weight portion; and a second concave portion that is formed at a position opposite to the beam portions and is deeper than the first concave portion.

Abstract: A nonstop program system includes program sides each including programs accomplishing the required function of the system and a dedicated variable area storing variables used for executing the program. Those programs are independent of each other and have the same contents. When the operational state of one program side is set to an ACT state, while using the one program side as the active side for executing the program in the one program side, the operational state of another program side is set to a HOT_SBY state, and a variable area of the other program side is synchronized with the variable area of the active side, thereby alternately and periodically switching the operational states of the program sides. When switching the active side, the operational state of the other program side is switched to the ACT state to cause the other program side as the active side to continuously execute the program.

Abstract: There is provided an electronic part that has a substrate, an insulating layer formed on the substrate and a pad formed on the insulating layer and is electrically connected with an external terminal and that further includes a cavity formed at least at either one of the substrate corresponding to a bottom surface of the electrode pad and a region of the insulating layer. It provides a highly reliable electronic part, its fabrication method as well as an acceleration sensor using the electronic part and its fabrication method.