Abstract: An operational amplifier has an input stage that branches a first current according to first and second input signals. An output stage generates an output signal from a second current and one of the branch currents in the input stage. A first transistor supplies the first current to the input stage. A second transistor supplies the second current to the output stage. A first gate line supplies a first bias potential to the gate terminal of the first transistor. A second gate line supplies a second bias potential to the gate terminal of the second transistor. The first gate line and the second gate line are electrically isolated from each other, preventing unwanted feedback of the output signal to the input stage by leakage through the gate lines.

Abstract: A detecting device has: a detecting element to which a first constant voltage is applied; a resistance element connected to the detecting element; a switching element having a first terminal to the resistance element, a second terminal controlled to a second constant voltage lower than the first constant voltage, and a control terminal sets the first terminal and the second terminal in a conducting state; a control unit, according to a conducting/non-conducting state, controls voltage to the control terminal to maintain a potential difference between the detecting element and the resistance element; and an AD converter converting, into a digital value, a potential of a potential difference between the first constant voltage and the first terminal being voltage-divided at the detecting element and the resistance element to the detecting element, a first reference potential is the first constant voltage, and a second reference potential is voltage to the first terminal.

Abstract: A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages.

Abstract: A timer circuit is provided with a comparator CMP1, a control unit and a comparator CMP2. The comparator CMP1 compares a potential of the capacitance element with the potential of a reference voltage VREF_H, and if the potential of the capacitance element reaches the potential of the reference voltage VREF_H, outputs a pre-specified time-up signal. The control unit performs control such that the potential of the capacitance element is higher than a potential of a reference voltage VREF_S, which is higher than the ground potential and lower than the potential of the reference voltage VREF_H. The comparator CMP2 compares the potential of the capacitance element with the potential of the reference voltage VREF_S, and if the potential of the capacitance element is lower than the potential of the reference voltage VREF_S, outputs a short circuit detection signal indicating that a short circuit state of the capacitance element has been detected.

Abstract: There is provided a constant current driven oscillating circuit including: an oscillator with first and second ends; a first field effect transistor that turns ON when a signal of a lower level than a first threshold voltage is input to a first gate terminal, and outputs, from a second terminal, current that has been input from a first terminal; a second field effect transistor turning ON when a signal output from the oscillator and is at a higher level than a second threshold voltage is input to a second gate terminal connected to the second end of the oscillator, and outputs, from a fourth terminal, current that has been input from a third terminal connected to the second terminal and to the first end of the oscillator; and an adjusting section that adjusts the first threshold voltage according to the level of the signal output from the oscillator.

Abstract: An acceleration sensor includes a weight; a base portion, a beam; and a piezo resistance element. The weight is arranged to displace upon receiving acceleration. The base portion is disposed around the weight apart from the weight. The beam has one end portion connected to the weight and the other end portion connected to the base portion. The beam also has a thick layer portion and a thin layer portion having a thickness smaller than that of the thick layer portion. The piezo resistance element is disposed over the thick layer portion and the thin layer portion.

Abstract: An operational amplifier that can suppress lowering of the current driving capability while performing a self adjustment of the common mode voltage is disclosed. A common mode voltage adjusting transistor and an auxiliary transistor are connected in parallel with a low-voltage side drive transistor of each of push-pull amplifying circuits that produce first and second amplified difference signals having different polarities in accordance with drive signals obtained by level-shifting a difference signal indicating a difference value of the levels of the first and second input signals by predetermined values. Current drive capabilities during a period of outputting said first and second amplified difference signals and a common mode voltage adjusting period respectively are increased by driving said auxiliary drive transistor by alternately using the drive signal obtained by level-shifting the difference signal and a common mode voltage adjusting signal.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate—such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.

Abstract: A standard cell, placed between a power rail and a ground rail in an integrated circuit, has active areas with connecting arms that extend beneath the power rail and ground rail. The connecting arms conduct current between the power and ground rails and the source regions of transistors in the active areas. The connecting arms include segments extending from these source regions to points beneath the power and ground rails, and segments running longitudinally beneath the power and ground rails. The connecting arms replace metal wiring that would otherwise be required, enabling the size of the standard cell to be reduced.

Abstract: The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the side surfaces is positioned at a boundary between the first area and the second area, a plurality of pads formed over the main surface of the semiconductor substrate and a plurality of external connecting terminals formed thereon, which are respectively electrically connected to the pads, a first resin portion which is formed over the main surface of the semiconductor substrate so as to cover the pads and has a main surface and side surfaces, and which is formed in such a manner that the external connecting terminals are exposed from the main surface and each of the side surfaces is positioned at the boundary, and a second resin portion which is positioned in the second area and formed so as to cover the side surfaces of the s

Abstract: A motion vector search apparatus has two internal memories for storing one macroblock of current image data each and N internal memories for storing M macroblocks of reference image data each, where M and N are integers greater than one. Selectors feed data from one of the current image memories and N?1 of the reference image memories to a processor that carries out a block matching calculation, on the basis of which a detector finds a motion vector for the selected macroblock of current image data. During the search, data for one new current image macroblock and M new reference image macroblocks are read into the non-selected memories, so that as soon as the motion vector is found, the search for the next motion vector can begin.

Abstract: A multi-input operational amplifier circuit operable with a high degree of accuracy and in a small area, a D/A converter using the multi-input operational amplifier circuit, and a drive circuit or driver for a display device, using the D/A converter. In embodiments of the multi-input operational amplifier circuit, a constant current source of a third differential amplifier circuit that causes a doubled constant current i×2 to flow with respect to constant current sources of first and second differential amplifier circuits by application of two types of bias voltages thereto is configured using PMOS of the same number and size. Therefore, operations equivalent to those of a conventional circuit may be realized by the three constant current source PMOSs, and a smaller chip size may be required.

Abstract: A drive circuit includes a plurality of output drive terminals and a plurality of push-pull circuit stages. Each of the push-pull circuit stages includes a pair of complementary transistors having a common terminal connected to a respective output drive terminal. The drive circuit further includes a plurality of first transistors connected in series with at least one of the pair of complementary transistors of the push-pull circuit stages, respectively, and a common second transistor. The common second transistor is connected with each of the plurality of first transistors to form a current mirror circuit. The drive circuit further includes a mirror current setting circuit for setting a mirror current flowing through the common transistor.

Abstract: The present invention provides a synchronizing signal detection circuit capable of always stably detecting a synchronizing signal. The synchronizing signal detection circuit predicts detection positions of synchronizing pulses every synchronization cycle peculiar to an input video signal. The synchronizing signal detection circuit further supplies the input video signal to a plurality of unnecessary signal eliminating paths in common and extracts synchronizing signals of every path respectively from video signals of every path obtained by eliminating unnecessary signals according to the characteristics of the paths every path.

Abstract: A COF package having a tape substrate including external input terminals and external output terminals provided in a chip non-mounting area, input wirings connected to the external input terminals respectively, output wirings connected to the external output terminals respectively, internal input wirings which are provided from the chip non-mounting area to a chip mounting area and provided between the input wirings and which are connected to the external input terminals, respectively, and a dummy wiring provided from the chip non-mounting area to the chip mounting area and provided between the internal input wirings; and a semiconductor chip including input electrodes connected to the input wirings respectively, output electrodes connected to the output wirings respectively, internal input electrodes connected to the internal input wirings respectively, and a dummy electrode provided spaced from each input electrode along one side of the chip surface, and connected to the dummy wiring.

Abstract: A receiving apparatus may achieve optimal RF and IF gain control while suppressing saturated amplification due to interference. The receiving apparatus includes an RF variable gain Amp that amplifies a received RF signal, a mixer that converts an output signal of the RF variable gain Amp into an IF signal, an IF variable gain Amp that amplifies the IF signal, a demodulator that demodulates an output signal of the IF variable gain Amp, and an AGC circuit. The AGC circuit sets a period of gain control for the RF variable gain Amp to be shorter than a period of gain control for the IF variable gain Amp when gains of the RF variable gain Amp and the IF variable gain Amp are controlled based on the output signal of the IF variable gain Amp.

Abstract: A semiconductor device includes a package substrate having a front surface and a backside surface; an electrode pad formed on the front surface; an outer connection pad formed on the backside surface and electrically connected to the electrode pad; a semiconductor chip mounted on the front surface and having an electrode electrically connected to the electrode pad; a sealing resin layer having a through hole formed with a die-molding and reaching the electrode pad for sealing the semiconductor chip; and a through electrode filled in the through hole with a conductive material and having one end portion electrically connected to the electrode pad and the other end portion exposed from the sealing resin layer.

Abstract: To provide a semiconductor substrate whose columnar member for alignment is difficult to fall off and a manufacturing method thereof. An alignment mark 24 (columnar member for alignment) and protection posts 26 surrounding the alignment mark 24 to protect the alignment mark are disposed in an alignment mark forming region 14 of a semiconductor wafer 101 (semiconductor substrate). Each of the protection posts has a diameter (maximum diameter) of, for example, 0.6 ?m. The protection posts 26 are arranged such that the diameter of each of the columnar protection posts 26 is greater than a diameter (for example, 0.2 ?m) of the alignment mark 24. That is, the protection posts 26 are arranged such that the contact area between each of the protection posts 26 and an underlayer thereof (dummy wire layer 22) is greater than the contact area between the alignment mark 24 and an underlayer thereof (dummy wire layer 22).

Abstract: A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on the first semiconductor chip having a second terminal pad. The first semiconductor chip is connected to the first pattern by a first bonding wire. The second semiconductor chip is connected to the second pattern by a second bonding wire, which connects the second pattern to the relay pad, and a third bonding wire, which connects the relay pad to the second terminal pad. The lengths of the first, second and third bonding wire are approximately the same.

Abstract: A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit, selects the first voltage and, when supplying a power supply voltage to an internal device, selects the second voltage; and a step-up circuit that, when the first voltage selected by the selector is input, boosts the first voltage to a third voltage and outputs the third voltage as the power supply voltage to the drive circuit and, when the second voltage selected by the selector is inputted, boosts the second voltage to a fourth voltage and outputs the fourth voltage as the power supply voltage to the internal device.