Abstract: In a non-volatile semiconductor memory device having a MONOS structure, a memory cell section for storing information, and a periphery circuitry section for writing and reading the information with respect to the memory cell section are formed in the surface region of a silicon substrate. A plurality of memory cells is formed in the memory cell section, while a plurality of periphery circuitry transistors are formed also in the periphery circuitry section. Since the periphery circuitry transistor has a structure wherein no electric charge accumulation layer exists, it is possible to prevent from electric charge injection to the periphery circuitry transistor, whereby hot carrier characteristics of the periphery circuitry transistor are improved.

Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.

Abstract: A display driver circuit for driving a current-controlled light-emitting device to emit light with a luminance gradation includes a memory for storing compensation data based on a measured value of a threshold voltage of a transistor for driving the light-emitting device, a register for holding the data to be displayed, and a data line driver for measuring the threshold voltage of the transistor through a data line connected to the transistor to produce the compensation data and store the compensation data in the memory and correcting the data to be displayed held in the register with the compensation data stored in the memory to output the gradation signal to the data line. Thus, the display driver circuit can be smaller in size than conventional circuitry which has a separate analog-to-digital converter.

Abstract: A diversity reception device includes branches, a controller and a combining section. Each branch includes a correlation section that generates a correlation signal that represents a correlation between a received signal and a delayed signal or between the received signal and a reference signal, where the correlation signal level disregarding the received signal level, a time position detector that detects time positions at which the level of the correlation signal is at a peak, a demodulation section that demodulates the received signal, and a multiplication section that multiplies the demodulated signal with a weighting factor. The controller controls the weighting factor on the basis of the respective levels of the correlation signals at the detected time positions. The combining section combines, by adding, the respective demodulated signals of the branches subsequent to the demodulated signal of each branch being multiplied with the weighting factor.

Abstract: An information processing device includes: a receiving unit that receives information to be processed that includes valid data, that has processing content information and identification information, and start information; and a control unit that controls an apparatus such that an initial processing is executed on the basis of the processing content information, and, if the identification information is included in the information to be processed, controls the apparatus such that processing that follows the initial processing is executed, and, if the identification information is not included in the information to be processed, controls the apparatus such that the processing that follows the initial processing is not executed.

Abstract: The Present invention provides a correlator including, a read-out processing circuit that reads out an OFDM signal in RAM as 2n?1 number of delay OFDM signals that are increased and delayed sequentially with their adjusted read-out timings. Complex conjugate circuits that outputs complex conjugates of the inputted nth to 2n?1th delay OFDM signals. Complex arithmetic circuits that perform complex multiplication to inputted original OFDM signal, the first to n?1th delay OFDM signals, and the output signals from the complex conjugate circuits. Moving average processing circuits take the moving average of the GI length, gain adjustment circuits adjust the gains, an adder circuit adds the outputs of the adjustment circuits, and a filter circuit smoothes the addition result. A control circuit variably controls the delay of the delay OFDM signals, the gains of the gain adjustment circuits, and the band characteristic of the filter circuit.

Abstract: A dropper-type regulator capable of providing a soft start function using a simple circuit configuration. An exemplary regulator includes a first FET having a relatively high current driving capability and a second FET having a relatively low current driving capability are provided in parallel between an input terminal and an output terminal. For a predetermined time immediately after power activation, only the second FET is driven, thereby preventing a large rush current. A switch circuit connected to the gate of the first FET is operated after the predetermined period of time, thereby supplying a driving voltage to the gate of the first FET.

Abstract: A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film.

Abstract: To improve connection reliability of a through electrode in a semiconductor device, and prevent deterioration of electrical characteristics due to a residue generated from a pad at the time of forming the through electrode. A contact area between a pad and a conductor layer is equal to a diameter of a hole of an opening provided in a silicon substrate. Consequently, it is possible to increase the contact area as compared with a conventional configuration. This improves the connection reliability. Furthermore, a residue containing metal is attached to the outside of an insulation film in the manufacturing process. Consequently, the residue is prevented from contacting a silicon substrate body. Also, heavy metals, such as Cu, in the residue are prevented from being diffused into the silicon substrate body. Therefore, it is possible to prevent the deterioration of electrical characteristics.

Abstract: Disclosed is a semiconductor device which includes a base substrate; a lower electrode formed on a main surface of the base substrate; and an insulating film formed over the lower electrode and the main surface of the base substrate. The insulating film has a contact hole defined by a wall extending upwardly from the top surface of the lower electrode. The insulating film has a film density distribution in which a film density decreases with increasing distance from the main surface of the base substrate in the thickness direction. A width of the contact hole increases as the film density decreases.

Abstract: An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously.

Abstract: A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage.

Abstract: Disclosed herein is a semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal.

Abstract: The present invention provides a MOSFET capable of improving the basic performance of a transistor such as saturation current characteristics, input follow-up and an offleak current at high levels, and a manufacturing method thereof.

Abstract: An apparatus for performing processing of an input acoustic signal to be reproduced by a loudspeaker, which generates a harmonic of a low pitch sound component equal to or lower than a predetermined low cutoff frequency, and generates a harmonic synthesized acoustic signal synthesizing the input signal with the harmonic. The apparatus generates an output acoustic signal which cuts off, from the harmonic synthesized acoustic signal, a low pitch sound component equal to or lower than the low cutoff frequency and a high pitch sound component equal to or higher than the high cutoff frequency. The apparatus sets a low and high cutoff frequencies in accordance with an output characteristic of a loudspeaker.

Abstract: A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder.

Abstract: A frequency synthesizer device that includes two modulation paths and suitably adjusts the amplitude of a control voltage that is outputted from a digital-to-analog converter (DAC) to a voltage-controlled oscillator. The frequency synthesizer device is provided with a voltage-controlled oscillator, a programmable frequency divider, a frequency phase comparator, a DAC, a switch and a modulation frequency displacement correction circuit. The voltage-controlled oscillator oscillates at an oscillation frequency depending on an input voltage. The programmable frequency divider frequency-divides a signal from the voltage-controlled oscillator. The frequency phase comparator outputs a phase difference between the frequency-divided signal and a reference clock. The DAC outputs an adjustment voltage. The switch connects the voltage-controlled oscillator to a reference voltage power source at a time of correction of the adjustment voltage.

Abstract: A USB test circuit for use in a USB device such as a system LSI with a USB function for testing the USB function generates and outputs a packet to be measured for a signal quality test. In the test circuit, a test signal including a test_sin signal carrying operation mode information is inputted via a serial interface to a serial interface block, and a packet to be measured is generated by a data pattern generation block and a transmission data delivery block depending on the operation mode information. The packet to be measured is outputted via a UTMI interface to a USB PHY layer. Thus, a packet to be measured for a signal quality test is generated and outputted without receiving packets not to be measured such as a SETUP packet and a DATA packet, thereby reducing the test time.

Abstract: The present invention comprises a semiconductor chip, and a semiconductor device having a plurality of semiconductor chips, that enables ESD protection from another semiconductor chip without increasing the chip area in case the semiconductor chip is Multi-Chip-Packaged, without wasting chip area in case the semiconductor chip is not Multi-Chip-Packaged. The exemplary semiconductor chip of the present invention includes an internal circuit and a first electrode pad electrically connected to a ground bus line of the first semiconductor chip in a region where an electrode pad, which gives and receives electric signals required for an operation of the internal circuit, cannot be provided.

Abstract: A PHS mobile phone set is provided with an offset estimation device which estimates an offset of a signal received through digital communication and makes use of the estimated offset as correction information for offset correction. The received signal is corrected in offset by use of the estimated offset and then demodulated. In the offset estimation device, the estimated offset is updated on the basis of the control signal indicating whether or not the demodulated digital signal is reliable.